Abstract: An asynchronous to synchronous converter is disclosed which produces clock pulses in synchronism with data bits of a non-return-to-zero code having a variable data rate. The converter comprises a first bit clock generator which is adapted to produce a first timing signal for the first bit clock pulse of a data pulse which is one or more bits in width. The bit width is measured separately for high level and low level data pulses and the timing signal is generated accordingly. It also comprises a second bit clock generator which produces successive timing signals, one for each additional bit width, according to the maximum allowable number of bits per data pulse. Means are provided for compensating for systematic error in measured bit widths such as caused by ink spread variations. Additionally, means are provided to insert a bit clock pulse in the event of a missing pulse in the bit clock stream. Also, a digital noise rejection means is provided.