Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre-and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: Compute clustering software embodied in a computer-readable medium and operable to provide a graphical user interface (GUI) is provided, the GUI operable to present a selection area for illustrating a plurality of receptors in a chassis, each receptor configured to couple to a network device, wherein the selection area conveys a physical location of each of the plurality of receptors, receive information from a user to create a defined cluster by pointing and clicking on a portion of the plurality of receptors illustrated in the selection area, present an image selection window with a plurality of software image choices, receive an image selection for each of one or more selected receptors in the defined cluster, and wherein the software is operable to associate each logical address of the defined cluster with a not necessarily same selected one of the plurality of images.

Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.

Abstract: A method of forming a barrier/liner for ferroelectric memory capacitors includes chemical vapor depositing 15 to 40 A of a first layer including a refractory metal nitride over a substrate having a plurality of metal-oxide-semiconductor (MOS) gate structures, ferroelectric memory (FeRAM) capacitors, and vias in a dielectric layer overlying the substrate. The first layer is treated using a first plasma treatment including exposing the first layer to a plasma in an atmosphere substantially-free of hydrogen. A 15 to 40 A thick second refractory metal nitride layer is chemical vapor deposited of over the first layer. The second layer is treated using a second plasma treatment including exposing the second layer to a plasma in an atmosphere substantially-free of hydrogen.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.

Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.

Abstract: Compute clustering software embodied in a computer-readable medium and operable to provide a graphical user interface (GUI) is provided, the GUI operable to present a selection area for illustrating a plurality of receptors in a chassis, each receptor configured to couple to a network device, wherein the selection area conveys a physical location of each of the plurality of receptors, receive information from a user to create a defined cluster by pointing and clicking on a portion of the plurality of receptors illustrated in the selection area, present an image selection window with a plurality of software image choices, receive an image selection for each of one or more selected receptors in the defined cluster, and wherein the software is operable to associate each logical address of the defined cluster with a not necessarily same selected one of the plurality of images.