Abstract: A method for estimating Doppler spread in mobile wireless communication devices, for example in CDMA or W-CDMA cellular communication systems, with improved noise immunity. The Doppler spread estimation is based on an estimated value of an autocorrelation or autocovariance at a first lag (210) and at a second lag (220), the magnitude of which is greater than the first lag. A first ratio is determined (250) between a first difference (230) and a second difference (240). The estimated Doppler spread is generally proportional to a square root (260) of the first ratio, and is scaled (270) by a multiplicative factor that depends on whether the estimated function is an autocorrelation or autocovariance function.

Abstract: A method for estimating Doppler spread in mobile wireless communication devices, for example in CDMA or W-CDMA cellular communication systems, with improved noise immunity. The Doppler spread estimation is based on an estimated value of an autocorrelation or autocovariance at a first lag (210) and at a second lag (220), the magnitude of which is greater than the first lag. A first ratio is determined (250) between a first difference (230) and a second difference (240). The estimated Doppler spread is generally proportional to a square root (260) of the first ratio, and is scaled (270) by a multiplicative factor that depends on whether the estimated function is an autocorrelation or autocovariance function.

Abstract: According to the present disclosure, an parallel formatted data signal is applied to an input (300), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (606) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (706), the delayed second signal is applied to a second parallel-to-serial converter (708), and first and second bit-serial data streams are produced. A controller (710) synchronizes an Arithmetic Logic Unit (616) to the first and second bit-serial data streams so that the ALU (616) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.

Abstract: Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Abstract: According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Abstract: A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.