Patents by Inventor John Paul Traver

John Paul Traver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11755227
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens
  • Patent number: 11579799
    Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mark Ish, Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao
  • Publication number: 20220374159
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 24, 2022
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens
  • Patent number: 11385820
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens
  • Publication number: 20220171702
    Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: Antonio David Bianco, John Paul Traver
  • Patent number: 11275679
    Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonio David Bianco, John Paul Traver
  • Publication number: 20210294522
    Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: Mark Ish, Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao
  • Publication number: 20210278985
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens
  • Publication number: 20210200669
    Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Antonio David Bianco, John Paul Traver