Patents by Inventor John Pavelka

John Pavelka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887924
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: January 30, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • Publication number: 20230088252
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 23, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
  • Patent number: 11562952
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 24, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
  • Publication number: 20220246514
    Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 4, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
  • Publication number: 20210111131
    Abstract: A semiconductor device may include an integrated circuit die and a thin metal layer applied and conformed to one or more surfaces of the integrated circuit die in order to shield active circuitry of the integrated circuit die from light.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 15, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: John PAVELKA, David PATTEN
  • Patent number: 8852513
    Abstract: Systems and methods are provided for packaging integrated circuit (IC) gas sensor systems that employ at least one gas sensor that is formed as part of an integrated circuit and configured to sense the presence and/or concentration of a target gas or other gas characteristics that may be present in the ambient gaseous environment surrounding the packaged IC gas sensor system.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 7, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Raymond Speer, Leon Cavanagh, Peter Smith, John Pavelka
  • Patent number: 7679162
    Abstract: An integrated current sensor package includes an integrated circuit having a coil in a metal layer of the circuit. A wire is placed close enough to the coil such that the coil and the wire are inductively coupled with each other.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: March 16, 2010
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, John Pavelka
  • Patent number: 7362086
    Abstract: A current sensor includes coupled inductors that generate an output current responsive to a detected current. The coupled inductor is implemented in an integrated circuit. An integrator circuit generates a sensed voltage responsive to the output current.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: April 22, 2008
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy J. Dupuis, John Pavelka
  • Publication number: 20070139066
    Abstract: An integrated current sensor package includes an integrated circuit having a coil in a metal layer of the circuit. A wire is placed close enough to the coil such that the coil and the wire are inductively coupled with each other.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Inventors: Timothy Dupuis, John Pavelka
  • Publication number: 20070139032
    Abstract: A current sensor includes coupled inductors that generate an output current responsive to a detected current. The coupled inductor is implemented in an integrated circuited. An integrator circuit generates a sensed voltage responsive to the output current.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Inventors: Timothy Dupuis, John Pavelka
  • Publication number: 20070096816
    Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 3, 2007
    Inventors: Susanne Paul, Timothy Dupuis, John Pavelka
  • Publication number: 20050242897
    Abstract: A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.
    Type: Application
    Filed: June 6, 2005
    Publication date: November 3, 2005
    Inventors: Lysander Lim, David Welland, John Pavelka, Edmund Healy