Abstract: A turbine engine may include a compressor section of the turbine engine. The turbine engine may include a combustion section of the turbine engine. The combustion section may be downstream of the compressor section. The turbine engine may include a turbine section of the turbine engine. The turbine section may be downstream of the combustion section. The turbine engine may include a sensor for speed detection. The sensor may be disposed at an upstream segment of the turbine section. The sensor may include a cooling jacket. The cooling jacket may encase at least a portion of the sensor. A cooling fluid may be in fluid communication with the cooling jacket and an outer surface of the sensor. The cooling jacket may be shaped to direct cooling fluid around the sensor.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.