Patents by Inventor John Philip Tero

John Philip Tero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7561092
    Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: July 14, 2009
    Assignee: Sigma Designs, Inc.
    Inventor: John Philip Tero
  • Publication number: 20080136688
    Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increase accuracy without significant increasing power consumption and size.
    Type: Application
    Filed: January 24, 2008
    Publication date: June 12, 2008
    Inventor: John Philip Tero
  • Patent number: 7379010
    Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: May 27, 2008
    Assignee: Sigma Designs, Inc.
    Inventor: John Philip Tero