Patents by Inventor John Pierson WADDEN

John Pierson WADDEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11055257
    Abstract: The present disclosure relates to systems and methods for automatically optimizing a reporting architecture of an application. In one implementation, a system for automatically optimizing a reporting architecture of an application may include a memory storing instructions and an automata processor configured to execute the instructions. The instructions may include identifying one or more state transition elements in the application; determining if two or more state transition elements have disjoint character sets; grouping two or more state transition elements having disjoint character sets into one or more groups; merging state transition elements included in the one or more groups; and outputting a merged report configured for disambiguation on a second processor.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 6, 2021
    Assignee: University of Virginia Patent Foundation
    Inventors: John Pierson Wadden, Kevin Alan Angstadt
  • Publication number: 20180330014
    Abstract: The present disclosure relates to systems and methods for automatically optimizing a reporting architecture of an application. In one implementation, a system for automatically optimizing a reporting architecture of an application may include a memory storing instructions and an automata processor configured to execute the instructions. The instructions may include identifying one or more state transition elements in the application; determining if two or more state transition elements have disjoint character sets; grouping two or more state transition elements having disjoint character sets into one or more groups; merging state transition elements included in the one or more groups; and outputting a merged report configured for disambiguation on a second processor.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Applicant: University of Virginia Patent Foundation d/b/a University of Virginia Licensing & Ventures Group
    Inventor: John Pierson WADDEN
  • Patent number: 9977652
    Abstract: Disclosed embodiments include systems, methods, and computer-readable media for generating pseudo-random numbers. Disclosed embodiments may receive, by the at least one processor, range data indicating a range of numbers. Disclosed embodiments may generate, based on the range data and by the at least one processor, a digitized finite state machine configured to produce pseudo-random output within the range of numbers. Further, disclosed embodiments may provide, by the at least one processor to a specialized pattern-matching device, programmable instructions to implement the digitized finite state machine on the specialized pattern-matching device. Disclosed embodiments may transmit, by the at least one processor to the specialized pattern-matching device, a pseudo-random bit stream for processing by the digitized finite state machine. Disclosed embodiments may receive, by the at least one processor from the specialized pattern-matching device, pseudo-random output from the digitized finite state machine.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 22, 2018
    Assignee: University of Virginia Patent Foundation
    Inventors: John Pierson Wadden, Nathan James Brunelle
  • Publication number: 20170083288
    Abstract: Disclosed embodiments include systems, methods, and computer-readable media for generating pseudo-random numbers. Disclosed embodiments may receive, by the at least one processor, range data indicating a range of numbers. Disclosed embodiments may generate, based on the range data and by the at least one processor, a digitized finite state machine configured to produce pseudo-random output within the range of numbers. Further, disclosed embodiments may provide, by the at least one processor to a specialized pattern-matching device, programmable instructions to implement the digitized finite state machine on the specialized pattern-matching device. Disclosed embodiments may transmit, by the at least one processor to the specialized pattern-matching device, a pseudo-random bit stream for processing by the digitized finite state machine. Disclosed embodiments may receive, by the at least one processor from the specialized pattern-matching device, pseudo-random output from the digitized finite state machine.
    Type: Application
    Filed: April 6, 2016
    Publication date: March 23, 2017
    Inventors: John Pierson WADDEN, Nathan James BRUNELLE