Abstract: A power filter circuit is provided for use in a package substrate for integrated circuits. A first power isolation circuit, having a first inductance, is configured to isolate power provided to one or more die connectors for provision to an integrated circuit die. A second power isolation circuit, having a second inductance, is configured to isolate power provided to one or more printed circuit board (PCB) connectors for provision to a PCB. A power plane electrically connects a first end of the first power isolation circuit to a first end of the second power isolation circuit, forming a “?” power filtering structure in some embodiments. A de-coupling capacitor can be provided as a surface-mount capacitor, or as an embedded capacitor in a core layer of an integrated circuit package.

Abstract: A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.

Abstract: A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.

Abstract: Methods and apparatus for canceling pre-cursor inter-symbol interference (ISI) are disclosed. In a digital communication system, a significant amount of noise can be attributed to the pre-cursor portion of the ISI. In a receiver, it can be relatively difficult to compensate for pre-cursor ISI in part because pre-cursor ISI is a result of one or more symbols that have yet to arrive at the receiver. One embodiment removes a portion of this ISI by using multiple detection thresholds in parallel. For example, data slicing (generation of a hard decision) can include three thresholds. These thresholds for slicing include a positive offset, a negative offset and no offset. The positive and negative offsets can correspond to the expected pre-cursor component of the data channel for which the data is transmitted or to a fraction thereof. The path with the correctly-compensated ISI is selected later.