Abstract: A power, ground and communication architecture (100) utilizes hubs (105, 110, 115). Each hub (105, 110, 115) contains computing, communication and power management elements (135, 140). Hubs (105, 110, 115) may be connected to multiple other hubs (105, 110, 115) to distribute communication and power in a freeform web-type arrangement, specific tree, bus or star arrangements are not required. Standardized wiring harness segments (120) are used to join the hubs (105, 110, 115) and control elements. Each of the strands in the web may be an independent point-to-point bus and isolated power line.

Abstract: The disclosed embodiments may relate to vehicle (10) having a control system (12) located within the vehicle (10). The control system (12) may include a processor (26) and a wake-up circuit (46) coupled to the processor (26). The processor (26) may utilize a program (34) during a standby mode of operation. The program (34) is configured to provide a voltage to the wake-up circuit (46) for a first time period (T1) once an interrupt is received by the processor (26). Then, the program (34) may monitor the wake-up circuit (46) for a second time period (T2). If a response of the wake-up circuit (46) exceeds at least one of a plurality of predetermined limits, then the program (34) may recalibrate the wake-up circuit (46).

Abstract: Observing an object within a visual blind spot of a motor vehicle includes using a mirror with at least one motor mechanically coupled thereto. Preferably, a position of the side view mirror can be adjusted by the at least one motor. An object detector detects objects within a visual blind spot of a vehicle. The object detector is operable to provide a detection signal to the at least one motor to adjust a position of the mirror to provide a view of the blind spot to a driver of the vehicle. The view can be toggled between normal viewing and blind spot viewing depending on the detection signal. The view can also be adjusted to track the object.

Abstract: A power, ground and communication architecture (100) utilizes hubs (105, 110, 115). Each hub (105, 110, 115) contains computing, communication and power management elements (135, 140). Hubs (105, 110, 115) may be connected to multiple other hubs (105, 110, 115) to distribute communication and power in a freeform web-type arrangement, specific tree, bus or star arrangements are not required. Standardized wiring harness segments (120) are used to join the hubs (105, 110, 115) and control elements. Each of the strands in the web may be an independent point-to-point bus and isolated power line.

Abstract: A system and method for charging an auxiliary battery (107) that drives an auxiliary load (109) includes a regulator (111', 223) coupled to an auxiliary battery (107). The regulator (111', 223) provides a charge current (121') that is variable dependent on a parameter of a control signal (203). Preferably, the parameter is an amplitude. A switch (113') provides a coupling and a decoupling between the auxiliary battery (107) and the auxiliary load (109). A control device (115') decouples the auxiliary battery (107) from the auxiliary load (109) via the switch (113'), and then provides the control signal (203) to the regulator (111', 223). By effecting this action, the regulator (111', 223) provides the variable charge current (121') to the auxiliary battery (107) dependent on the amplitude of the control signal (203).

Abstract: A method of and a circuit for temperature protecting a transistor (4) comprising:a controlled voltage supply (34) for applying to the transistor a first voltage substantially less than a predetermined voltage required to render the transistor conductive at normal temperature;a detector (8, 12, 18) for detecting whether the transistor conducts in response to the applied first voltage; anda controlled voltage supply (46), responsive to not detecting conduction of the transistor, for enabling the transistor by applying thereto a second voltage at least equal to the predetermined voltage, and, responsive to detecting conduction of the transistor, for disabling the transistor by removing the first voltage therefrom and inhibiting the application of the second voltage thereto so as to prevent damage thereto.

Abstract: A first signal (V.sub.1) related to FET drain to source voltage and a second signal (V.sub.2) related to FET source current are compared and the FET (11) is turned off when the first signal exceeds the second signal by a predetermined amount. This corresponds to turning the FET off whe the drain to source on resistance of the FET exceeds a FET on resistance value corresponding to a maximum allowable FET die temperature. Thus the FET is turned off for excessive due temperatures to prevent damage to the FET. A start-up circuit (41, 42) is provided to insure proper initial turning on of the FET, and a short circuit protection circuit (30) is provided for turning the FET off it the source current exceeds some maximum current limit. Accurate, effective monitoring of the FET die temperature is provided without the use of an additional temperature sensing element provided adjacent the FET.