Abstract: A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: A technique for controlling the oxidation of silicon is achieved by applying low temperature ammonia prior to the oxidation. The result is that the subsequent oxidation of the silicon is at a slower oxidation rate and higher nitrogen content. The higher nitrogen content is particularly beneficial for a gate dielectric because it acts as somewhat of a boron barrier and provides additional resistance to unwanted oxidation. The result is transistors with improved gate dielectric thickness uniformity across a wafer for a tighter threshold voltage distribution, reduced shift in threshold voltage, and improved time to breakdown.

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer.In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region.

Abstract: A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.

Abstract: An improved process is disclosed for forming the field oxide which provides isolation between adjacent devices in an integrated circuit. In one embodiment of the invention the improvement includes implanting halogen ions, and preferably chlorine ions, into the selected regions of a semiconductor substrate where field oxide is to be formed. The halogen ions are implanted before the field oxide is thermally grown and result in a localized enhancement of the oxide growth rate in the vertical direction compared to the lateral direction. For a given oxidation cycle, the halogen implant results in the growth of a thicker oxide with minimum lateral encroachment.

Abstract: A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.

Abstract: A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

Abstract: A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.

Abstract: A process is disclosed for fabricating a semiconductor device which includes a trench formed at the surface of the device substrate. The surface of the device substrate is oxidized and the oxide is patterned to form an opening which exposes a portion of the underlying surface. Ions are implanted through the opening and into the surface to form a damaged surface region which is coincident with the opening and extends under the edge of the oxide. A trench is etched by reactive ion etching using the opening in the oxide as an etch mask. The substrate, including the walls of the trench and the ion implant damaged surface portion under the edge of the oxide, is thermally oxidized. The oxidation rate is enhanced by the damage and causes a thicker oxide to grow in the damaged region which forms a collar around the intersection of the trench with the surface.