Abstract: A method of manufacturing an active matrix substrate (1) comprising a row and column array of active elements (10) wherein each element (11) is associated with a TFT (13) having a gate electrode (306) connected to a corresponding row conductor (15) and source (320) and drain (321) electrodes connected to corresponding column conductors (14), and ESD protective circuitry (20) connected to at least one of the row conductors for protecting the TFTs against electrostatic discharge (ESD). The method comprising the steps of forming semiconductor regions of the TFTs (302) and the ESD protective circuitry (303); depositing gate electrodes (306) of the TFTs and corresponding row conductors (15); and depositing source (320) and drain (321) electrodes of the TFTs and corresponding column conductors (14), wherein the ESD protective circuitry (20) is operative to control ESD prior to deposition of the column conductors (14).

Abstract: A charge pump circuit (1) comprises a series of voltage boosting stages (11), each stage (11) comprising a switching means (10) and a capacitive element (12) connected in series between the input to the stage and a respective voltage control terminal (14,15). The voltage control terminals (14,15) comprise at least two groups of terminals receiving respective timed control voltages, and adjacent stages (11) are associated with different terminal groups. The switching means (10) of one or more stages (11) comprises a lateral PIN junction diode. The use of diodes enables the charge pump circuit itself to operate from a lower supply voltage than is possible with the use of TFTs. The use of lateral PIN diodes enables the charge pump circuit to be formed using the same processing as may be required for TFT's of the circuit to which the boosted voltage is supplied. This enables the charge pump circuit to be formed on a common substrate with higher voltage TFT circuitry for, for example, an AMLCD.

Abstract: A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).

Abstract: A charge pump circuit (1) comprises a series of voltage boosting stages (11), each stage (11) comprising a switching means (10) and a capacitive element (12) connected in series between the input to the stage and a respective voltage control terminal (14,15). The voltage control terminals (14,15) comprise at least two groups of terminals receiving respective timed control voltages, and adjacent stages (11) are associated with different terminal groups. The switching means (10) of one or more stages (11) comprises a lateral PIN junction diode. The use of diodes enables the charge pump circuit itself to operate from a lower supply voltage than is possible with the use of TFTs. The use of lateral PIN diodes enables the charge pump circuit to be formed using the same processing as may be required for TFT's of the circuit to which the boosted voltage is supplied. This enables the charge pump circuit to be formed on a common substrate with higher voltage TFT circuitry for, for example, an AMLCD.

Abstract: A large-area electronic device, such as an AMLCD, has switching TFTs (T.sub.p) in a matrix and circuit TFTs (T.sub.s) in a peripheral drive circuit. Both the TFTs (T.sub.p, T.sub.s) comprise a field-relief region (130) which has a lower doping concentration (N-) than their drain region (113) and which is present between their channel region (111) and the drain region (113). This field-relief region (130), at least over most of its length, overlaps with the gate (121) in the circuit TFTs (T.sub.s) so as to reduce series resistance in the field-relief region (130) by conductivity modulation with the gate (121). However, the drain region (113) in the switching TFTs (T.sub.p) is offset from overlap with their gate (121) by at least most of the length of their field-relief region (130). This field-relief offset permits the switching TFTs (T.sub.p) to have a lower leakage current than the circuit TFTs (T.sub.s).

Abstract: In an LCD or other electronic device, thin-film circuit elements on a substrate (100) form a sample-and-hold or other sampling circuit (10). The circuit (10) comprises a TFT (Ts) as a sampling transistor and preferably another TFT (T2) to compensate for displacement currents in charging and discharging the insulated gate (12) of the sampling TFT. Even when T2 is included, a slow drift in output voltage (Vo) is observed when Ts switches off, and this limits use of the circuit, especially in large area active-matrix devices. In accordance with the invention this slow drift is removed or significantly reduced by injecting minority carriers into the channel region of Ts (and T2) from a doped opposite-type region (119) or Schottky contact region (119) which is forward biased via a thin-film supply line (129). The minority carriers neutralise majority carriers which are being slowly released by thermal emission from trapping states in the TFT body.

Abstract: In the manufacture of a large-area electronic device (e.g. an active-matrix liquid-crystal display or other flat panel display), a TFT of improved lifetime stability results from the inclusion of a field-relief region (22) which is of lower doping concentration than the drain region (12) and which is formed in an area (2) of lateral separation between the channel region (21) and the drain region (22). An energy beam (40), e.g. from an excimer laser, is used to provide the field-relief region (22), by laterally diffusing the doping concentration of the drain region (12) along an area (2) of the semiconductor film (20) significantly larger than the thickness of the semiconductor film (20). The method is simple and easily controllable, an advantageous doping profile (FIG. 3b) is obtained along the field-relief region (22) by this lateral diffusion.

Abstract: A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the density of charge carrier traps. Source and drain electrodes (6 and 7) contact opposite ends (5a,5b) of the channel region (5), and a gate electrode (8) is provided at one major surface (4a) of the semiconductor layer (4) for controlling a conduction channel of one conductivity type in the polycrystalline channel region (5) to provide a gateable connection between the source and drain electrodes (6 and 7). An area (50) of the polycrystalline channel region (5) spaced from the electrodes (6,7,8) of the transistor (1) and lying adjacent to the other major surface (4b) of the semiconductor layer (4) is doped with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent to the other major surface (4b).