Patents by Inventor John R. Behnke

John R. Behnke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6995437
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery
  • Patent number: 6780708
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 24, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery
  • Patent number: 6409879
    Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Toprac, John R. Behnke, Matthew Purdy
  • Patent number: 6245581
    Abstract: The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: June 12, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas Bonser, Anthony J. Toprac, Matthew Purdy, John R. Behnke, James H. Hussey, Jr.
  • Patent number: 6133132
    Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: October 17, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony J. Toprac, John R. Behnke, Matthew Purdy