Patents by Inventor John R. Camagna
John R. Camagna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9197423Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.Type: GrantFiled: February 14, 2008Date of Patent: November 24, 2015Assignee: AKROS SILICON, INC.Inventors: Philip John Crawley, Amit Gattani, John R. Camagna, Jun Cai
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Patent number: 9191216Abstract: Embodiments of the present invention provide a power source equipment (PSE) network device operable to provide a network signal that may include both power and data. This PSE network device includes a network connector and an integrated circuit. The network connector physically couples the PSE network device to the network. The integrated circuit further includes a power feed circuit. This power feed circuit is operable to combine and pass the received data signals and power signal as a single network signal. A PSE controller electrically couples to the integrated circuit but is not necessarily part of the integrated circuit. The PSE controller is operable to govern the production and distribution of the power portion of the network signal.Type: GrantFiled: October 13, 2005Date of Patent: November 17, 2015Assignee: AKROS SILICON, INCInventors: John R. Camagna, Sajol Ghoshal, J. Francois Crepin
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Patent number: 9189036Abstract: In a network device, a connector module comprises a network connector coupled to the connector module in a configuration that transfers power and communication signals and an application connector that comprises serial media independent interface (SMII) pins and power pins. A Power-over-Ethernet (PoE) circuit is coupled between the network connector and the application connector.Type: GrantFiled: April 24, 2007Date of Patent: November 17, 2015Assignee: AKROS SILICON, INC.Inventors: Sajol Ghoshal, John R. Camagna, Philip John Crawley
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Patent number: 9185834Abstract: A network device comprises an Ethernet physical layer (PHY) comprising an isolation, protection, and electromagnetic interference suppression barrier operative for isolated power and data transfer.Type: GrantFiled: April 24, 2007Date of Patent: November 10, 2015Assignee: AKROS SILICON, INC.Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Patent number: 7923710Abstract: A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge.Type: GrantFiled: March 8, 2007Date of Patent: April 12, 2011Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Patent number: 7761719Abstract: In a network device, a connector module comprises a network connector coupled to the connector module in a configuration that transfers power and communication signals and an application connector that comprises serial media independent interface (SMII) pins and power pins. A Power-over-Ethernet (PoE) circuit is coupled between the network connector and the application connector.Type: GrantFiled: May 31, 2006Date of Patent: July 20, 2010Assignee: Akros Silicon Inc.Inventors: Sajol Ghoshal, John R. Camagna
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Patent number: 7685452Abstract: Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs produce a second power signal which may be supplied to the Ethernet network. The active control circuits sense the second power signal passed by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the sensed power signal. At least one twisted pair couples to each differential transistor pair's output node and is operable to pass the Ethernet power signal.Type: GrantFiled: November 23, 2005Date of Patent: March 23, 2010Assignee: Akros Silicon Inc.Inventors: John R. Camagna, Philip Crawley, Sajol Ghoshal
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Patent number: 7620825Abstract: Embodiments of the present invention provide a network device operable to receive a network signal that may include both power and data from a coupled network. This network device includes a network connector and an integrated circuit. The network connector physically couples the network device to the network. An optional protection circuit may provide surge protection or incoming network signals received by the network device through the network connector. An optional switching/rectifying circuit sees the output of the protection circuit and is operable to rectify a power signal when contained within the network signal. The integrated circuit further includes a power feed circuit conductively coupled to the protection circuit and the rectifying circuit. This power feed circuit is operable to separate and pass the received data signal to a network physical layer and separate and pass the received power signal to a power management module.Type: GrantFiled: August 19, 2005Date of Patent: November 17, 2009Assignee: Akros Silicon Inc.Inventors: John R. Camagna, Sajol Ghoshal, Francois Crepin
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Publication number: 20090265563Abstract: Embodiments of the present invention provide a network device operable to receive a network signal that may include both power and data from a coupled network. This network device includes a network connector and an integrated circuit. The network connector physically couples the network device to the network. An optional protection circuit may provide surge protection or incoming network signals received by the network device through the network connector. An optional switching/rectifying circuit sees the output of the protection circuit and is operable to rectify a power signal when contained within the network signal. The integrated circuit further includes a power feed circuit conductively coupled to the protection circuit and the rectifying circuit. This power feed circuit is operable to separate and pass the received data signal to a network physical layer and separate and pass the received power signal to a power management module.Type: ApplicationFiled: August 19, 2005Publication date: October 22, 2009Inventors: John R. Camagna, Sajol Ghoshal, J. Francois Crepin
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Publication number: 20090207538Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventors: Philip John Crawley, Amit Gattani, John R. Camagna, Jun Cai
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Patent number: 7500118Abstract: In a network device, a power potential rectifier is adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal and data signal received from the network connector. The power potential rectifier regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.Type: GrantFiled: November 21, 2005Date of Patent: March 3, 2009Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, John R. Camagna
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Patent number: 7500116Abstract: The present invention provides a method to at least partially power an Ethernet device from a plurality of balanced network power signals received through a network connection. This involves attaching the network device to the network, wherein network signals are received and contain both power signals and/or data signals. These network signals may be passed through surge protection and power-conditioning circuitry wherein the output of these circuits may be provided to a power absorbing circuit. This power absorbing circuit may separate the communication signal and power signal from the network signal. The communication signal may be passed to a network physical layer while the power signal may be passed to a power distribution module. Additionally, because certain embodiments may provide multiple pairs of network power signals to the power absorbing circuit, the current or power associated with each power signal must be sensed and balanced. This may be done with an active control circuit.Type: GrantFiled: August 23, 2005Date of Patent: March 3, 2009Assignee: Akros Silicon Inc.Inventors: John R. Camagna, Sajol Ghoshal
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Patent number: 7469348Abstract: Dynamic insertion insertion loss for an ethernet power on differential cable pairs is shown in a power feed circuit that supplies power to a network attached device (PD). An insertion loss control circuit limits power loss in a coupled power feed circuit. determines an insertion loss limit, and senses an average power of the power signals to produce a common mode feedback signal to the power feed circuit.Type: GrantFiled: August 19, 2005Date of Patent: December 23, 2008Assignee: Akros Silicon, Inc.Inventors: John R. Camagna, Phillip John Crawley
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Publication number: 20080267212Abstract: A network device comprises an Ethernet physical layer (PHY) comprising an isolation, protection, and electromagnetic interference suppression barrier operative for isolated power and data transfer.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Publication number: 20080218258Abstract: A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Philip John Crawley, Sajol Ghoshal, John R. Camagna
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Publication number: 20080144248Abstract: A network interface apparatus is disclosed that includes a connector coupled to a plurality of communication lines. A Physical Layer (PHY) device coupled to the communication lines and to a first ground level. A transient event suppression module coupled between the communication lines and a low impedance path to earth ground. During a transient event the transient event suppression module provides a low impedance path to the earth ground to protect the PHY device from the transient event. A power circuit that delivers power from a second ground level to the PHY device is coupled to the first ground level. The first ground level and the second ground level are coupled to provide a low impedance path during normal operation and high impedance during transient events.Type: ApplicationFiled: February 23, 2007Publication date: June 19, 2008Inventors: Philip John Crawley, John R. Camagna, Charles Cai
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Patent number: 7368798Abstract: Embodiments of the present invention provide an integrated circuit (IC) having an integrated DC-DC power converter therein. This IC is operable to support the distribution of combined power and data signals in a network environment such as an Ethernet network according to protocols such as the power over Ethernet (PoE) protocol. The IC includes a DC-DC power converter, a power feed circuit, and a network physical layer (PHY) module, wherein the PHY module may contain fine line structures susceptible to damage when exposed to excessive voltages. To prevent or reduce the likelihood of damage to the PHY module from voltages supplied to the DC-DC power converter, a common substrate ground is shared between the IC components.Type: GrantFiled: November 18, 2005Date of Patent: May 6, 2008Assignee: Akros Silicon Inc.Inventors: John R. Camagna, Sajol Ghoshal
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Publication number: 20060218420Abstract: Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs produce a second power signal which may be supplied to the Ethernet network. The active control circuits sense the second power signal passed by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the sensed power signal. At least one twisted pair couples to each differential transistor pair's output node and is operable to pass the Ethernet power signal.Type: ApplicationFiled: November 23, 2005Publication date: September 28, 2006Inventors: John R. Camagna, Philip Crawley, Sajol Ghoshal
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Patent number: 6707868Abstract: A digital timing recovery system wherein the rate conversion is independent of the sampling rate, and which may be set in a network mode or a remote mode. The invention includes a transceiver core for processing transmit and receive data at a predetermined baud rate, an analog front end for transmitting and receiving analog signals over a network, a phase detector for generating a phase error estimate and a timing controller for receiving the phase error estimate signal and generating a receive and transmit phase control signal for controlling timing of the analog front end. A selector is provided for selecting a remote mode of operation or a network mode of operation.Type: GrantFiled: April 12, 1999Date of Patent: March 16, 2004Assignee: Intel CorporationInventors: John R. Camagna, James Ward Girardeau, Jr., Stanley K. Ling, Hiroshi Takatori
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Patent number: 6249557Abstract: A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.Type: GrantFiled: March 3, 1998Date of Patent: June 19, 2001Assignee: Level One Communications, Inc.Inventors: Hiroshi Takatori, Stanley K. Ling, Amit Gattani, John R. Camagna