Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

Abstract: A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: An N-bit bus includes (N?1) bidirectional interfaces to couple to (N?1) bidirectional signal lines to exchange (transmit and receive) signals between companion devices. The bus includes two unidirectional signal line interfaces. The first is a unidirectional receive interface to couple to a unidirectional signal line to receive signals from the companion device. The second is a unidirectional transmit interface to couple to a unidirectional signal line to transmit signals to the companion device. The bus provides N signal lines for the N-bit bus in each direction, with an additional “backwards facing” signal line. The backwards facing signal line can allow the devices to prepare for a switch in the direction of the N-bit bus.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: In embodiments, a device includes an input interface to receive a broadcast command from a host computer, the broadcast command including an access mode indication, and decoding circuitry coupled with the interface. The decoding circuitry is to determine, based at least in part on the received access mode indication, that the broadcast command is directed to access one or more pre-defined setup or control registers of one or more devices, or to access one or more internal registers of the one or more devices, and, in response to the determination, implement the access to the setup or control registers, or to the one or more internal registers. In embodiments, the device is disposed on a memory module coupled to the host computer.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.