Abstract: A surgical bur for use in cutting bone includes a stem adapted to selectively couple to an attachment tube of a micro-burring instrument assembly and is configured for selective rotation upon activation of the micro-burring instrument. The surgical bur includes a plurality of cutting flutes disposed at a distal end of the stem which defines a corresponding number of clearance surfaces disposed therebetween. Each of the cutting flutes includes a cutting edge and a trailing edge. One or more push-off elements is defined in the clearance surface between adjacent pairs of cutting flutes of the plurality of cutting flutes, the push-off elements being configured to contact bone during rotation of the surgical bur and being configured to deflect the surgical bur relative thereto and optimize the cutting efficiency and effectiveness of the surgical bur based on the rotational speed (RPM) thereof.

Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Abstract: A three zone rapid thermal processing system includes three arrays of radiant heating lamps for heating a semiconductor wafer. The arrays are positioned along the axis of the wafer such that one array is adjacent one face of the wafer, the second array is adjacent the second face of the wafer and the third array is adjacent the edge of the wafer. A wafer holder holds the wafer face transverse to the common axis of the radiant heating lamps. Reflectors at each array reflect radiant heat onto the wafer. The arrays are independently connected to power sources and a controller to provide efficient coupling of the heat sources and a uniform temperature distribution across a wafer.

Abstract: A conical rapid thermal processing system includes a conical thermal radiation reflector and a plurality of elongated radiant heating sources within the conical thermal radiation reflector. The elongated radiant heating sources pass through an imaginary conical surface within the conical thermal radiation reflector. A wafer holder within the imaginary conical surface holds the wafer face transverse to the common axis of the conical reflector and the conically arranged radiant heating lamps. The conical thermal radiation reflector and conically arranged lamps provide uniform radiant heating across the face of a wafer without significantly degrading coupling efficiency.

Abstract: A CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed. In CMOS SRAM cells with small feature sizes, single event errors result from ion interactions with transistor drains on the side of a cell holding a low voltage. The configuration of the cell presents a high impedance between these low voltage drains and the low voltage gate on the opposite side of the cell, while presenting a high impedance between corresponding components with high voltages. The SRAM cell is protected from single event errors while minimizing the increase in switching speed which accompanies any increase in internal cell impedance.

Abstract: A multijunction solar cell is disclosed which uses a patterned intercell ohmic connection as the tunnel junction to connect a top solar cell in electrical and optical series with a bottom solar cell. By confining this patterned tunnel junction to shadowed areas directly beneath the top surface metallization grid, the tunnel junction is set free from the requirement that it be transparent and have band gaps greater than or equal to those of the top solar cell.