Patents by Inventor John R. Hauser

John R. Hauser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240382224
    Abstract: A surgical system having adaptive control includes a surgical cutting device, at least one sensor, and a controller. The surgical cutting device includes a cutting tool and a motor configured to drive movement of the cutting tool. The at least one sensor is configured to produce sensor data indicative of at least one property of the surgical cutting device during use. The controller is configured to receive the sensor data and determine a performance condition of the surgical cutting device based at least on the sensor data. The controller is further configured, where the determined performance condition is an adverse performance condition, to at least one of: adjust settings of the surgical cutting device or recommend a change relating to use of the surgical cutting device.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 21, 2024
    Inventors: Michael Vu, Milton F. Barnes, Jaffar Hleihil, Aayush Malla, Andrew J. Wald, Mahin Maharjan, Saideep Nakka, Haoran Li, Sophie A. Pervere, Bret R. Hauser, John W. Kulas
  • Patent number: 6472233
    Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: October 29, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khaled Z. Ahmed, Nguyen D. Bui, Effiong Ibok, John R. Hauser
  • Patent number: 5418885
    Abstract: A three zone rapid thermal processing system includes three arrays of radiant heating lamps for heating a semiconductor wafer. The arrays are positioned along the axis of the wafer such that one array is adjacent one face of the wafer, the second array is adjacent the second face of the wafer and the third array is adjacent the edge of the wafer. A wafer holder holds the wafer face transverse to the common axis of the radiant heating lamps. Reflectors at each array reflect radiant heat onto the wafer. The arrays are independently connected to power sources and a controller to provide efficient coupling of the heat sources and a uniform temperature distribution across a wafer.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: May 23, 1995
    Assignee: North Carolina State University
    Inventors: John R. Hauser, Furman Y. Sorrell, Jimmie J. Wortman
  • Patent number: 5253324
    Abstract: A conical rapid thermal processing system includes a conical thermal radiation reflector and a plurality of elongated radiant heating sources within the conical thermal radiation reflector. The elongated radiant heating sources pass through an imaginary conical surface within the conical thermal radiation reflector. A wafer holder within the imaginary conical surface holds the wafer face transverse to the common axis of the conical reflector and the conically arranged radiant heating lamps. The conical thermal radiation reflector and conically arranged lamps provide uniform radiant heating across the face of a wafer without significantly degrading coupling efficiency.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: October 12, 1993
    Assignee: North Carolina State University
    Inventors: Jimmie J. Wortman, Furman Y. Sorrell, John R. Hauser, Mark J. Fordham
  • Patent number: 4805148
    Abstract: A CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed. In CMOS SRAM cells with small feature sizes, single event errors result from ion interactions with transistor drains on the side of a cell holding a low voltage. The configuration of the cell presents a high impedance between these low voltage drains and the low voltage gate on the opposite side of the cell, while presenting a high impedance between corresponding components with high voltages. The SRAM cell is protected from single event errors while minimizing the increase in switching speed which accompanies any increase in internal cell impedance.
    Type: Grant
    Filed: November 22, 1985
    Date of Patent: February 14, 1989
    Inventors: Sherra E. Diehl-Nagle, John R. Hauser
  • Patent number: H667
    Abstract: A multijunction solar cell is disclosed which uses a patterned intercell ohmic connection as the tunnel junction to connect a top solar cell in electrical and optical series with a bottom solar cell. By confining this patterned tunnel junction to shadowed areas directly beneath the top surface metallization grid, the tunnel junction is set free from the requirement that it be transparent and have band gaps greater than or equal to those of the top solar cell.
    Type: Grant
    Filed: May 14, 1987
    Date of Patent: September 5, 1989
    Assignee: The United States of America as represented by the Secretaryof the Air Force
    Inventors: Salah M. Bedair, Robert J. Markunas, Michael L. Timmons, James A. Hutchby, John R. Hauser