Abstract: A structure of a circuitry substrate for securing an area from tampering is disclosed. The structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. The top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.

Abstract: A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.

Abstract: A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.

Abstract: A low voltage silicon bipolar RF (radio frequency) receiver front end includes a low noise preamplifier and double-balanced mixer. The receiver incorporates monolithic microstrip transformers for significant improvements in performance compared with silicon broadband designs. Reactive feedback and coupling elements are used in place of resistors to lower the front end noise figure through the reduction of resistor thermal noise, and this also allows both circuits to operate at supply voltages below 2 volts. Circuits fabricated using 0.8 .mu.m Bipolar CMOS technology provide a peak npn transistor transit frequency f.sub.T of 11 GHz. At a supply voltage of 1.9 volts, the measured input third order intercept point is +2.3 dBm with a 10.9 dB single-sideband noise figure. Power dissipated is less than 5 mW. The low noise amplifier input intercept is -3 dBm with a 2.8 dB noise figure and 0.5 dB gain. Power dissipation of the preamplifier is less than 4 mW from a 1.9 V supply.

Abstract: In methods and apparatus for aligning the phase of a local clock signal with the phase of a data signal, an incoming data signal is delayed to provide a delayed data signal and regenerated with a local clock signal to provide a regenerated data signal. A difference between the phase of the delayed data signal and the phase of the regenerated data signal is detected. The phase of the local clock signal is retarded by a predetermined fraction of a bit period if the regenerated data signal leads the delayed data signal and is advanced by the predetermined fraction of the bit period if the regenerated data signal lags the delayed data signal. The retiming, detecting, retarding and advancing steps are repeated continuously to obtain and maintain approximate alignment of the phase of the local clock signal with the phase of the delayed data signal. The methods and apparatus are useful in high speed packet switches.

Abstract: In known thin film switch controlled matrix multiplexed liquid crystal displays (LCD's), alternating pulses of an applied waveform are of reverse polarity. If the transient behaviour characteristic of the switches controlling the LCD is not saturated during application of a selection pulse, the selected pels may experience a relatively low RMS voltage in the ON state. To ensure that selected pels are fully turned on, the addressing waveform proposed consists of a series of pulses of one polarity followed by a corresponding series of pulses of opposite polarity. Transient effects are minimized by applying the series of unipolar pulses and the pels are consequently subjected to a high RMS voltage. However, net DC current through the LC is still zero as required in order to guard against irreversible electrochemical degradation of the LC. The higher RMS voltage can be used to improve contrast ratio or to increase the level of multiplexing.

Abstract: A hollow molded unitary plastic pallet is provided for use in handling and transporting cargo, particularly with forklift trucks. The pallet comprises upper and lower surfaces with legs disposed on the lower surface. Reinforcement of the pallet is achieved by means of holes through the pallet surfaces and by means of reinforcing grooves disposed on the legs and on the lower surface of the pallet. The grooves on the lower surface extend from the holes to the legs and continue down along the length of the legs to their bases.