Abstract: An embodiment of a bus management device permits scheduling of transactions to allow concurrent execution of the transactions. Data bus usage is scheduled by setting shift register bits. Each position in the shift register corresponds to one clock cycle. When a current transaction is in a data phase, the value in the shift register is used to determine when to begin a control phase of the next transaction so that a desired number of idle clock cycles are present between data bus usage time periods for successive transactions.

Abstract: Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel display. Transferring data through the single frame buffer by interleaving reads and writes includes (1) alternately writing to the frame buffer and reading from the frame buffer portions of each bit-plane of a sequence bit-plane data; and (2) writing to said frame buffer so as to replace each said portion of a bit-plane in the frame buffer with a corresponding portion of a next bit-plane. By interleaving read and write accesses, a single frame buffer and less interface logic are necessary to transfer data from a storage device to a digital pixel display. In a three channel digital color pixel imaging device, this reduces the number of frame buffer SDRAM units from six to three, and significantly reduces the overall cost associated with implementing data flow through the data storage and frame buffer blocks.

Abstract: Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel display. Transferring data through the single frame buffer by interleaving reads and writes includes (1) alternately writing to the frame buffer and reading from the frame buffer portions of each bit-plane of a sequence bit-plane data; and (2) writing to said frame buffer so as to replace each said portion of a bit-plane in the frame buffer with a corresponding portion of a next bit-plane. By interleaving read and write accesses, a single frame buffer and less interface logic are necessary to transfer data from a storage device to a digital pixel display. In a three channel digital color pixel imaging device, this reduces the number of frame buffer SDRAM units from six to three, and significantly reduces the overall cost associated with implementing data flow through the data storage and frame buffer blocks.

Abstract: A printer including a memory configured to store executable code; a processor coupled to the memory and configured to execute executable code; a print mechanism coupled to the processor and configured to print an image in response to execution of executable code; a memory receptacle configured to removably receive a plug-in memory; and a memory controller configured to selectively write executable code onto a plug-in memory received by the memory receptacle.