Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.

Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: Memory with asymmetric power delivery for keeper cells in the memory are provided. In some embodiments, first and second power delivery circuits use separate first and second independently regulated power supplies. The first supply may be a supply nominally used for the memory structure, while the second supply may be lower than the first supply. In some embodiments, during a write operation, the first (higher) supply is used for one of the logic elements in a keeper cell, while the second (lower) supply is used for the other keeper logic element.

Abstract: An integrated circuit device includes a memory cell coupled to a supply voltage line to receive a supply voltage and a voltage control circuit operable to reduce a magnitude of the supply voltage prior to a write cycle to the memory cell. The voltage control circuit includes a first capacitor that is selectively coupled between a supply voltage line and a first reference supply voltage line of the integrated circuit device in anticipation of a write cycle to the memory cell.

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: An integrated circuit device includes a memory cell coupled to a supply voltage line to receive a supply voltage and a voltage control circuit operable to reduce a magnitude of the supply voltage prior to a write cycle to the memory cell. The voltage control circuit includes a first capacitor that is selectively coupled between a supply voltage line and a first reference supply voltage line of the integrated circuit device in anticipation of a write cycle to the memory cell.

Abstract: An apparatus for prealigning hex or square stock sections before chucking in a collet. As hex stock advances, pre-alignment bushing provides general alignment. A plurality of spring-loaded veliers positioned within the prealignment collar slidably contact the flats of the stock along the path of travel and urges the stock radially to the proper alignment, so that the points of the stock do not hit the collet.