Abstract: This disclosure provides techniques for processing an input signal while providing protection from differential power analysis. In one example, random delay units may receive the input signal, a random delay generator may generate random delay values, and the random delay units may add the random delay values to the input signal to generate delayed signals, such that each delayed signal is substantially desynchronized relative to one or more other delayed signals. Subsequently, processing units may process the delayed signals to generate delayed output signals, and random delay removal units may add additional delay values to the delayed output signals, such that each delayed output signal is substantially synchronized relative to other delayed output signals, to produce output signals. Finally, a combination unit may combine the output signals to generate a common output signal that corresponds to the input signal that is processed by any one of the processing units.

Abstract: This disclosure provides techniques for processing an input signal while providing protection from differential power analysis. In one example, random delay units may receive the input signal, a random delay generator may generate random delay values, and the random delay units may add the random delay values to the input signal to generate delayed signals, such that each delayed signal is substantially desynchronized relative to one or more other delayed signals. Subsequently, processing units may process the delayed signals to generate delayed output signals, and random delay removal units may add additional delay values to the delayed output signals, such that each delayed output signal is substantially synchronized relative to other delayed output signals, to produce output signals. Finally, a combination unit may combine the output signals to generate a common output signal that corresponds to the input signal that is processed by any one of the processing units.

Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.