Abstract: Computer system powered-off state auxiliary power rail control. At least some of the illustrative embodiments are systems configured to have: a first powered-off state in which the main output power signal is deactivated within the power supply and the auxiliary power output signal is active and coupled to an auxiliary power rail of the printed circuit board; and a second powered-off state in which the main power output signal is deactivated and the auxiliary power output signal is active and decoupled from the auxiliary power rail of the printed circuit board.

Abstract: Dissipating power from a power supply. At least some of the illustrative embodiments are motherboards including a printed circuit board configured to couple to a main processor (and the printed circuit board configured to couple to a main power signal and an auxiliary power signal of a power supply), and a power dissipation circuit on the printed circuit board. The power dissipation circuit is configured to detect that the main power signal has powered-off, and responsive to the detection dissipate power from the auxiliary power signal for a predetermined amount of time less than an amount of time needed to fully discharge the auxiliary power signal in the absence of alternating current (AC) power to the power supply.

Abstract: Regulating voltages. At least some of the illustrative embodiments are systems including a switching circuit configured to produce an intermediate voltage signal from an input voltage signal, and a first voltage regulator coupled the switching circuit and configured to produce a first regulated voltage signal from the intermediate voltage signal. The switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate voltage signal and the first regulated voltage signal.

Abstract: Computer system powered-off state auxiliary power rail control. At least some of the illustrative embodiments are systems configured to have: a first powered-off state in which the main output power signal is deactivated within the power supply and the auxiliary power output signal is active and coupled to an auxiliary power rail of the printed circuit board; and a second powered-off state in which the main power output signal is deactivated and the auxiliary power output signal is active and decoupled from the auxiliary power rail of the printed circuit board.

Abstract: A power regulator system and method are provided. In one embodiment, a power regulator system comprises a voltage regulator configured to generate a regulator voltage at a regulator node based on a feedback voltage and an output stage configured to generate a run voltage at a run voltage node and a standby voltage at a standby voltage node based on the regulator voltage. The system also comprises a mode control stage configured to set the power regulator system in one of a run mode and a standby mode in response to a mode signal and a feedback control stage configured to provide the feedback voltage based on the run voltage in the run mode and based on the standby voltage in the standby mode.

Abstract: Dissipating power from a power supply. At least some of the illustrative embodiments are motherboards including a printed circuit board configured to couple to a main processor (and the printed circuit board configured to couple to a main power signal and an auxiliary power signal of a power supply), and a power dissipation circuit on the printed circuit board. The power dissipation circuit is configured to detect that the main power signal has powered-off, and responsive to the detection dissipate power from the auxiliary power signal for a predetermined amount of time less than an amount of time needed to fully discharge the auxiliary power signal in the absence of alternating current (AC) power to the power supply.

Abstract: Regulating voltages. At least some of the illustrative embodiments are systems including a switching circuit configured to produce an intermediate voltage signal from an input voltage signal, and a first voltage regulator coupled the switching circuit and configured to produce a first regulated voltage signal from the intermediate voltage signal. The switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate voltage signal and the first regulated voltage signal.

Abstract: A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.

Abstract: An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Abstract: A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.

Abstract: An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Abstract: A pulse shaping circuit includes a series resistor and shunt capacitor that is switched from a finite capacitance value to a substantially open circuit in response to the voltage across the capacitor being on opposite sides of a threshold. The capacitor comprises a MOSFET having a gate connected to the resistor and a source drain path, connected to ground and +Vdd in first and second embodiments, respectively.

Abstract: An integrated circuit device is provided that has I/O bonding pads across the surface of the chip, where the I/O bonding pads can be electrically accessed via ancillary testing pads in order to perform functionality or other necessary tests prior to bump bonding formation without damaging the bonding pads or the underlying circuitry.

Abstract: A system and method for improving alpha-particle induced soft error rates in integrated circuits is provided. Logic isolation circuits implemented using a substantially fewer number of pn-junctions are situated at the outputs of fast logic portions containing a substantially greater number of pn-junctions. The present invention reduces the vulnerability of a dynamic logic circuit of incurring alpha soft errors by effectively trading the probability of an isolation circuit composed of only a few pn-junctions incurring alpha-particle strikes with the probability of a fast logic circuit having substantially more pn-junctions incurring alpha-particle strikes. By reducing the number of pn-junctions susceptible to alpha-particle strikes, the present invention significantly lowers the potential alpha-particle induced soft error rate.

Abstract: An apparatus and method are described for generating a plurality of clock edges from a reference clock signal. The clock edges which are generated are locked in phase with the reference clock signal. The edges may be at any integral or non-integral multiple of the reference clock frequency.

Abstract: An integrated circuit calculator which can operate in either a twelve digit or an eight digit mode is provided. A conditional modification circuit modifies some of the memory addresses employed in the twelve digit calculator to provide the eight digit calculator with more random access memory registers than the twelve digit calculator. In the twelve digit calculator, the conditional modification circuit also controls folding of some memory registers in order to minimize the chip area required for the memory cicuitry and control logic.