Abstract: A holographic optical interconnect system (100) and method (200) provide flexible, efficient interconnection of a plurality of circuit boards CBs and a plurality of integrated circuit chips. Each CB has at least an optically transparent substrate OTS mate parallel to the CB and extending outside a CB holder. Each OTS mate has parallel sides and carries at least two holographic optical elements HOEs. A first one of the HOEs on a first OTS mate reflects at least a predetermined portion of a first light beam transmitted by a transmitter on a corresponding CB to another HOE, which transmits a received light beam via free space outside the CB holder. On another OTS mate, two HOEs are utilized to receive and direct at least part of the light beam received to a detector on a corresponding CB via free space within the circuit board holder or reflection within the OTS mate.

Abstract: A digital cellular time-division multiple access (TDMA) system including a cellular switch and at least one base site employing 6:1 packing of transcoded information. The system incorporates the VSELP speech encoding algorithm to transcode data input from a cellular switch and a unique packing scheme to compress six messages channels worth of transcoded data into one 20 msec, 160 frame information block for transmission in one TDM timeslot. The compressed transcoded data is transmitted to a base-site on a T1 link where the six message channels worth of transcoded data is un-packed and coded. The coded information is then separated into two groups of three air-interface timeslots where two separate transmitters transmit one group each of three air-interface timeslots on two separate radio carrier frequencies.

Abstract: A scanning CRT graphics video display system is disclosed in which a graphics display controller reads formatted information signals into a refresh memory in a read-modify-wire mode and reads the stored information out of the refresh memory in a display mode. During the display mode the information in the memory is provided on a common data bus for sequential reading into four different shift registers having different bit capacities with the different bit capacities effectively implementing predetermined delays such that the shift registers will properly simultaneously read out the information that was sequentially loaded into the shift registers. A programmable logic sequencer provides address select signals in addition to address signals provided by the graphics display controller so as to address four different memory planes in the refresh memory, and the address select signals are also utilized to sequentially enable the loading of the four shift registers.

Abstract: A preconverged color display station is disclosed which is compatible with a computer controlled control unit that provides electrical convergence control signals. Compatibility is obtained by causing the control unit to transmit the electrical convergence signals to the screen storage memory RAM (random access memory) which normally stores information defining the character and character attributes to be visually provided by the display station CRT screen. The stored convergence signals are read back to the control unit from the screen RAM. After all of the convergence signals have been received by the display station and prior to the transmission of character and character attribute information signals to the screen RAM, the contents of the screen RAM is erased. Subsequently, the contents of the screen RAM, which now contains character display information signals, is read out and utilized to define a visual display on a CRT.

Abstract: A CRT in a CRT device is degaussed following a timed period of device inactivity and while the screen of the CRT is darkened, as well as at device turn-on or at manual activation. The screen stays darkened until data is inputted, and degaussing reoccurs during each subsequent timed period of inactivity.

Abstract: A preconverged color display station is disclosed which is compatible with a computer controlled control unit that provides electrical convergence control signals. Compatibility is obtained by causing the control unit to transmit the electrical convergence signals to the screen storage memory RAM (random access memory) which normally stores information defining the character and character attributes to be visually provided by the display station CRT screen. The stored convergence signals are read back to the control unit from the screen RAM. After all of the convergence signals have been received by the display station and prior to the transmission of character and character attribute information signals to the screen RAM, the contents of the screen RAM is erased. Subsequently, the contents of the screen RAM, which now contains character display information signals, is read out and utilized to define a visual display on a CRT.