Abstract: According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra “space” than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.

Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).

Abstract: A sensor assembly includes a sensor operable to sense a physical parameter and generate an electrical signal responsive to the sensed physical parameter. Local processing circuitry is physically positioned proximate the sensor and is electrically coupled to the sensor. The local processing circuitry includes an output port adapted to be coupled to a communications channel and the local processing circuitry is operable to process data from the sensor to generate processed sensor data and to provide the processed data on the output port.

Abstract: A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem to access desired storage locations within the memory subsystem.

Abstract: A device for generating an acoustic signal in a fluid includes an engine operable to repeat a thermodynamic process to vibrate a membrane of the engine to generate an acoustic signal having more than one period. The thermodynamic process includes heating mass inside a chamber of an engine to generate pressure inside the chamber; in response to generating the pressure, moving in a first direction a portion of a membrane of the engine; removing mass from inside the chamber to decrease the pressure inside the chamber; and in response to decreasing the pressure inside the chamber, moving the membrane portion in a second direction. Because the engine repeats the thermodynamic process, the engine can generate and sustain an acoustic signal for a significant amount of time.

Abstract: A device for generating an acoustic signal in a fluid includes an engine operable to repeat a thermodynamic process to vibrate a membrane of the engine to generate an acoustic signal having more than one period. The thermodynamic process includes heating mass inside a chamber of an engine to generate pressure inside the chamber; in response to generating the pressure, moving in a first direction a portion of a membrane of the engine; removing mass from inside the chamber to decrease the pressure inside the chamber; and in response to decreasing the pressure inside the chamber, moving the membrane portion in a second direction. Because the engine repeats the thermodynamic process, the engine can generate and sustain an acoustic signal for a significant amount of time.

Abstract: A device for generating an acoustic signal in a fluid includes an engine operable to repeat a thermodynamic process to vibrate a membrane of the engine to generate an acoustic signal having more than one period. The thermodynamic process includes heating mass inside a chamber of an engine to generate pressure inside the chamber; in response to generating the pressure, moving in a first direction a portion of a membrane of the engine; removing mass from inside the chamber to decrease the pressure inside the chamber; and in response to decreasing the pressure inside the chamber, moving the membrane portion in a second direction. Because the engine repeats the thermodynamic process, the engine can generate and sustain an acoustic signal for a significant amount of time.

Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).

Abstract: A technique for rendering non-linear BRDFs that are stable in both the temporal and spatial domains, without serious interruption to the content creation pipeline used in most games, is provided. Non-linear content is linearized by rendering in texture space at a fixed resolution. A MIP-map chain is calculated from this texture. The complete MIP-map chain is used for rendering on a display device. Low resolution reflectance parameters are used to approximate the highest resolution reflectance parameters as the object becomes smaller on the display device. The low resolution reflectance parameters are calculated using non linear fitting techniques.

Abstract: A platform with a sensor is for coupling to a submarine or other underwater vehicle and for sending data about the seascape to the submarine. In an embodiment, the platform is coupled to the submarine via a cable that has communication lines in it. The sensor may be attached to the platform via a mast. In an embodiment, the platform has a control surface, an anti-collision sensor, and a ballast. The platform allows a submarine to survey the seascape before rising to periscope depth.

Abstract: A projectile system includes an enclosure, first and second propellants and first and second projectiles. The first and second propellants are disposed within the enclosure. The first projectile is disposed within the enclosure between the first propellant and a first end of the enclosure, and is operable to exit the enclosure via the first end in response to detonation of the first charge. The second projectile is disposed within the enclosure between the second propellant and a second end of the enclosure, and is operable to exit the enclosure via the second end in response to the detonation of the second propellant.

Abstract: A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of the algorithm portions, each template defining a circuit for executing the respective algorithm portion, and interconnects the identified templates such that the interconnected templates define a circuit that is operable to execute the algorithm. As compared to prior design tools, this tool may decrease the time and effort required to design a circuit for instantiation on a programmable logic integrated circuit (PLIC) or on an application-specific integrated circuit (ASIC) by allowing one to construct the circuit from previously written templates that define previously tested and debugged circuits.

Abstract: A mission system includes a peer vector machine having a host processor and pipeline accelerator and including bridge objects that provide communication via signal objects, message objects, and mission objects.

Abstract: A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem to access desired storage locations within the memory subsystem.

Abstract: A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that compose the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often “fit” the circuit into the pipeline accelerator regardless of its composition.

Abstract: A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.

Abstract: According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra “space” than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.

Abstract: A sensor assembly includes a sensor operable to sense a physical parameter and generate an electrical signal responsive to the sensed physical parameter. Local processing circuitry is physically positioned proximate the sensor and is electrically coupled to the sensor. The local processing circuitry includes an output port adapted to be coupled to a communications channel and the local processing circuitry is operable to process data from the sensor to generate processed sensor data and to provide the processed data on the output port.

Abstract: A library includes one or more circuit templates and an interface template. The one or more circuit templates each define a respective circuit operable to execute a respective algorithm or portion thereof. And the interface template defines a hardware layer operable to interface one of the circuits to pins of a programmable logic circuit when the layer and the one circuit are instantiated on the programmable logic circuit. Such a library may shorten the time and reduce the effort that an engineer expends designing a circuit for instantiation on a PLIC or ASIC by allowing the engineer to build the circuit from templates of previously designed and debugged circuits.