Abstract: In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed.