Patents by Inventor John Reid Hauser, Jr.

John Reid Hauser, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power, high performance, heterogeneous, scalable processor architecture
    Patent number: 8386751
    Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Icelero LLC
    Inventors: Amit Ramchandran, John Reid Hauser, Jr.
  • Programmable processor architecture
    Publication number: 20110131393
    Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
    Type: Application
    Filed: May 18, 2010
    Publication date: June 2, 2011
    Applicant: 3PLUS1 TECHNOLOGY, INC.
    Inventors: Amit Ramchandran, John Reid Hauser, JR.
  • Low power, high performance, heterogeneous, scalable processor architecture
    Patent number: 7721069
    Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: May 18, 2010
    Assignee: 3Plus1 Technology, Inc
    Inventors: Amit Ramchandran, John Reid Hauser, Jr.