Abstract: The digital CMOS/LSI synchronous serial multiplier includes a register to store an X-bit sign magnitude multiplier in parallel. The digital multiplier number can be entered into the register either serially or in parallel. A serial N-bit 2's complement multiplicand input is provided. (X - 1) adder stages are connected in series. A control arrangement coupled to the register, the multiplicand input and the adder stages are provided to couple each of the magnitude bits of the multiplier number into a different one of the adder stages with the adder stages performing successive additions of the magnitude bits of the multiplier number to provide as an output of a last of the adder stages a serial product having M bits. A serial Y-bit 2's complement addend can be coupled to the first of the adder stages to add the addend to the product.

Abstract: This invention relates to a digital vocoder where speech is translated to a digital version thereof. An adaptive filter in the form of an N stage Itakura type cascade derives from the speech a prediction residual and N spectral parameter in the form of weighting coefficients of the filter. The pitch period, derived from the prediction residual, the voiced/unvoiced decision derived from the first of the weighting coefficients and the peak amplitude of a pitch pulse, and a digital signal representing filter gain, derived from the last of the weighting coefficients are multiplexed with each other and the N spectral parameters for transmission to a receiver. The receiver employs an excitation generator responsive to the pitch period, the gain signal and the voiced/unvoiced decision to produce an excitation signal to excite an N/2 cascade connected stage receive filter. Each stage of the receive filter operates on a time shared basis on an adjacent pair of the N spectral parameters.