Abstract: A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device consists of two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.

Abstract: A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device consists of two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract: A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device consists of two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.

Abstract: A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.

Abstract: A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.

Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.

Abstract: A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

Abstract: A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device includes two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.

Abstract: In a flat flex cable, signal lines are surrounded by logic ground planes above and below which are viaed together left and right. The ground planes coupled with the flex cable dielectric determine characteristic the impedance and attenuation of the cable and provide differential signal EMI shielding. All signal layers and logic ground planes are enclosed within the two outermost shield layers which are viaed together left and right and around the connectors to enclose both signal layers and logic ground planes to provide common mode EMI shielding.

Abstract: A flex cable pad on pad terminal structure is shown having raised connector pads formed using a rigid stiffener with raised features or bumps formed integral with the stiffener; aligned with the connector pad surfaces; and laminated to the flex cable surface opposite the surface presenting the exposed connector pad surfaces, to create raised contact pads that are not subject to relaxation over time when subjected to high contact normal forces. The use of a metal stiffener which has been coined to produce the raised features aligned with the contact pad locations and lamination using a film or layer of thermocuring adhesive affords an economical process and assembly technique that also effects hot deformation of the flex cable at the contact pad locations.