Patents by Inventor John Richard Hunt
John Richard Hunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10916429Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.Type: GrantFiled: December 5, 2019Date of Patent: February 9, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Patent number: 10886263Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: GrantFiled: September 29, 2017Date of Patent: January 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20200111671Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10535521Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: GrantFiled: March 8, 2019Date of Patent: January 14, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10515806Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: GrantFiled: March 8, 2019Date of Patent: December 24, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206683Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206684Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10276382Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: GrantFiled: June 6, 2017Date of Patent: April 30, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Publication number: 20190103386Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: William T. CHEN, John Richard HUNT, Chih-Pin HUNG, Chen-Chao WANG, Chih-Yi HUANG
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20180047571Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: ApplicationFiled: June 6, 2017Publication date: February 15, 2018Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Publication number: 20160233169Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventor: John Richard Hunt
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Patent number: 9343333Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.Type: GrantFiled: December 19, 2014Date of Patent: May 17, 2016Assignee: Advanced Semiconductor Engineering, Inc.Inventor: John Richard Hunt
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Publication number: 20150140737Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.Type: ApplicationFiled: December 19, 2014Publication date: May 21, 2015Inventor: John Richard Hunt
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Patent number: 8941222Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.Type: GrantFiled: November 11, 2010Date of Patent: January 27, 2015Assignee: Advanced Semiconductor Engineering Inc.Inventor: John Richard Hunt
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Publication number: 20120119373Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventor: JOHN RICHARD HUNT
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Publication number: 20110127654Abstract: A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC..,Inventors: Chaofu Weng, John Richard Hunt, Li Chuan Tsai, Yi Ting Wu, Chieh-Chen Fu, Ying-Te Ou