Patents by Inventor John Robert Abernathey

John Robert Abernathey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5672901
    Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: September 30, 1997
    Assignee: International Business Machines Corporation
    Inventors: John Robert Abernathey, Randy William Mann, Paul Christian Parries, Julie Anne Springer