Abstract: A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.

Abstract: A memory element programmable between different impedance states, comprising: a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor) and at least one other first electrode element; a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the switch layer by application of electric fields.

Abstract: A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.

Abstract: A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields.

Abstract: Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.

Abstract: A method can include determining a data value stored in a memory element of a memory cell array based on the length of time required to cause a property of the memory element to change. A memory device can include a plurality of elements programmable into at least two different states; and an electrical bias section that applies sense conditions to a selected element; and a sense section configured to distinguish between the two different states according to whether a change in property occurs in the selected element within a predetermined time under the sense conditions.

Abstract: A memory device, comprising: read circuits coupled to a plurality of memory elements programmable between at least two different resistance states, the read circuits generating output values based on resistance states of selected memory elements in a read operation; and current limit circuits that limit a current flow through each memory element to less than a program threshold current; wherein the program threshold current corresponds to a current that flows through a memory element being programmed to cause its resistance to change to a resistance between that of two different resistance states.

Abstract: Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

Abstract: A memory device can include a plurality of memory cells each comprising at least one programmable impedance memory element; a programming circuit coupled to the memory elements and configured to apply at least one time varying pulse to memory elements to place them into one of at least two different impedance states; and a programming voltage source coupled to the programming circuit configured to generate the at least one time varying pulse; wherein the time varying pulse decreases and increases in potential while having an overall increase in one voltage polarity.

Abstract: A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.

Abstract: A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields.

Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.

Abstract: A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.

Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.