Patents by Inventor John S. Bialas, Jr.
John S. Bialas, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10580476Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.Type: GrantFiled: January 11, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ryan P. King, Stephen Glancy, John S. Bialas, Jr.
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Publication number: 20190214073Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: RYAN P. KING, STEPHEN GLANCY, JOHN S. BIALAS, JR.
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Patent number: 10289578Abstract: In an example, a method includes monitoring a memory bus for one or more commands sent by a memory controller to a memory device and determining whether the one or more commands have a value indicating an operation mode of the memory device. Information associated with the one or more commands may be assessed based on the operation mode, and the information may be stored to one or more registers of the memory controller. The operation mode may be a per dynamic random access memory (DRAM) addressability (PDA) mode, a per buffer addressability (PBA) mode, or a per rank mode. Accessing the information may include a first set of configuration values in response to the value indicating the PDA mode or the PBA mode, and a second set of configuration values in response to the value indicating the per rank mode.Type: GrantFiled: September 1, 2015Date of Patent: May 14, 2019Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., Stephen P. Glancy
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Patent number: 10134455Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: GrantFiled: November 16, 2017Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Patent number: 10126968Abstract: In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.Type: GrantFiled: September 24, 2015Date of Patent: November 13, 2018Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., Stephen P. Glancy, Saravanan Sethuraman, Jacob D. Sloat
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Patent number: 9940417Abstract: Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected.Type: GrantFiled: July 21, 2016Date of Patent: April 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Bialas, Jr., Siva Pr. Boosa, Stephen P. Glancy, Yelena M. Tsyrkina
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Publication number: 20180075887Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: ApplicationFiled: November 16, 2017Publication date: March 15, 2018Inventors: John S. Bialas, JR., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Patent number: 9899067Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: GrantFiled: January 13, 2017Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Publication number: 20180025105Abstract: Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected.Type: ApplicationFiled: July 21, 2016Publication date: January 25, 2018Inventors: John S. BIALAS, JR., Siva Pr. BOOSA, Stephen P. GLANCY, Yelena M. TSYRKINA
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Patent number: 9691453Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.Type: GrantFiled: February 16, 2016Date of Patent: June 27, 2017Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Publication number: 20170178703Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.Type: ApplicationFiled: February 16, 2016Publication date: June 22, 2017Inventors: John S. Bialas, JR., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Publication number: 20170154660Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: ApplicationFiled: January 13, 2017Publication date: June 1, 2017Inventors: John S. Bialas, JR., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Patent number: 9627030Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: GrantFiled: February 16, 2016Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Patent number: 9620184Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.Type: GrantFiled: December 16, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Publication number: 20170090804Abstract: In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: John S. Bialas, JR., Stephen P. Glancy, Saravanan Sethuraman, Jacob D. Sloat
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Publication number: 20170060790Abstract: In an example, a method includes monitoring a memory bus for one or more commands sent by a memory controller to a memory device and determining whether the one or more commands have a value indicating an operation mode of the memory device. Information associated with the one or more commands may be assessed based on the operation mode, and the information may be stored to one or more registers of the memory controller. The operation mode may be a per dynamic random access memory (DRAM) addressability (PDA) mode, a per buffer addressability (PBA) mode, or a per rank mode. Accessing the information may include a first set of configuration values in response to the value indicating the PDA mode or the PBA mode, and a second set of configuration values in response to the value indicating the per rank mode.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventors: John S. Bialas, JR., Stephen P. Glancy
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Patent number: 9558850Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.Type: GrantFiled: December 1, 2015Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
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Patent number: 6097215Abstract: A voltage translation circuit translates an input signal having a first voltage level and a second voltage level to an output signal having the second voltage level and a third voltage level respectively. The voltage translation circuit according to the present invention includes a regenerative circuit having a first terminal and a second terminal. The voltage level at the first terminal increases responsive to the voltage level at the second terminal decreasing. The voltage level at the second terminal increases responsive to the voltage level at the first terminal decreasing. The voltage level at the first terminal defines the output signal. A first switch is coupled to the first terminal of said regenerative circuit, such that closing the first switch decreases the voltage level at the first terminal. A second switch is coupled to the second terminal of said regenerative circuit, such that closing the second switch decreases the voltage level at the second terminal.Type: GrantFiled: May 22, 1998Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: John S. Bialas, Jr., John E. Gersbach, Charles R. London
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Patent number: 5568380Abstract: A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.Type: GrantFiled: August 30, 1993Date of Patent: October 22, 1996Assignee: International Business Machines CorporationInventors: Timothy B. Brodnax, John S. Bialas, Jr., Steven A. King, Johnny J. LeBlanc, Dale A. Rickard, Clark J. Spencer, Daniel L. Stanley
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Patent number: 5525923Abstract: A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.Type: GrantFiled: February 21, 1995Date of Patent: June 11, 1996Assignee: Loral Federal Systems CompanyInventors: John S. Bialas, Jr., Joseph A. Hoffman