Patents by Inventor John S. Clapp, III

John S. Clapp, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847513
    Abstract: A current limiter circuit for limiting current in an electrical circuit element such as the magneto-resistive portion of a read head forming a portion of a hard disk drive and including: a first circuit connected to one end of the circuit element for applying a bias current of a desired value to the circuit element in response to the value to an input signal; a second circuit connected to the other end of the circuit element for setting the amplitude of the voltage signal generated across the circuit element in response to the bias current; and a third electrical circuit connected to both the first and second circuits for limiting the value of bias current to a predetermined level for an abnormal event such as a current surge, a short circuit, or any other type of undesired current operating condition.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: January 25, 2005
    Assignee: Agere Systems Inc.
    Inventors: John S. Clapp, III, Thanh Van Nguyen
  • Patent number: 6339319
    Abstract: An emitter or source follower is added to a current mirror and, more particularly, to a cascoded current mirror that uses beta helpers to reduce the mirror error due to base currents for restoring a Vbe of voltage compliance to the cascoded current mirror, thus allowing the use of a cascoded current mirror in applications where it could not otherwise be used due to voltage compliance problems.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: January 15, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: John S. Clapp, III
  • Patent number: 5539334
    Abstract: A voltage level shifter circuit (10) for outputting an output high (18) and output low (18) signal is provided which accommodates multiple power supplies (12 and 22) at different relative voltage to each other. The voltage level shifter (10) includes an input stage (24) which is characterized by voltage ranges applicable to the process used to make the circuit. The voltage level shifter circuit includes an output stage (18) which is also characterized by the same voltage ranges which cannot be exceeded. The output stage outputs the translated output high (16) and output low (18) voltage signals. A clamping network (20) is employed to ensure that the output stage voltage ranges are not exceeded. The present invention implements a high voltage level shifter (10) using low voltage components by extending the breakdown capability of the voltage level shifter circuit (10) past the breakdown voltage of any single component in the circuit.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: July 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: John S. Clapp, III, Wayne T. Chen
  • Patent number: 5467050
    Abstract: A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.
    Type: Grant
    Filed: January 4, 1994
    Date of Patent: November 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: John S. Clapp, III, Wayne T. Chen
  • Patent number: 5412531
    Abstract: A circuit (16) having an extended breakdown capability is provided for switching an inductive load driver (12). The circuit (16) includes a first switch (18) for providing a first drive voltage when the first switch (18) is closed. A second switch (20) is provided for receiving the first drive voltage from the first switch (18) and delivering the first drive voltage to the inductive load driver (12) when the second switch (20) is closed. The second switch (20) limits the voltage across the first switch (18) to a predetermined level when the first switch (18) is open. A third switch (22) provides a second drive voltage to the inductive load driver (12) when the third switch (22) is closed.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: May 2, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: John S. Clapp, III