Abstract: A physical arrangement of at least two power switches and at least one capacitor in a power loop. At least one of the switches is formed of at least two parallel electronic devices, such as transistors. The arrangement minimizes total power loop impedance and results in approximately equal impedance in each parallel branch of the switch formed of two parallel devices, thereby resulting in approximately equal currents in the switches.

Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: A physical arrangement of at least two power switches and at least one capacitor in a power loop. At least one of the switches is formed of at least two parallel electronic devices, such as transistors. The arrangement minimizes total power loop impedance and results in approximately equal impedance in each parallel branch of the switch formed of two parallel devices, thereby resulting in approximately equal currents in the switches.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit includes a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also include an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit comprises a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also comprise an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A circuit for an RF switch using FET transistors that largely cancels the non-linearity of the Coss of the FETs over a majority of the signal range, and reduces distortion. The RF switch includes two substantially identical FETs. The source of one FET is connected to the drain of the other FET and the node formed comprises one terminal of the switch. Two substantially identical capacitors are connected in series with each other and in parallel with the FETs, and the node thus formed comprises the second terminal of the switch. The capacitors are selected such that they have negligible impedance at AC frequencies for which the switch is expected be used, and in particular a much lower impedance than Coss of each FET. A voltage source with a series impedance is also connected in parallel with the capacitors and the two FETs.

Abstract: A circuit for an RF switch using FET transistors that largely cancels the non-linearity of the Coss of the FETs over a majority of the signal range, and reduces distortion. The RF switch includes two substantially identical FETs. The source of one FET is connected to the drain of the other FET and the node formed comprises one terminal of the switch. Two substantially identical capacitors are connected in series with each other and in parallel with the FETs, and the node thus formed comprises the second terminal of the switch. The capacitors are selected such that they have negligible impedance at AC frequencies for which the switch is expected be used, and in particular a much lower impedance than Coss of each FET. A voltage source with a series impedance is also connected in parallel with the capacitors and the two FETs.

Abstract: A high frequency, full bridge, resonant DC to DC converter provides a main DC output voltage that is regulated by adjusting the phase shift of the input power to a main input transformer and at least one additional DC output voltage that is regulated on the secondary side of the power input transformer. A main DC output voltage is regulated by a full bridge resonant switching converter with lossless switching of input power devices. At least one additional secondary winding on the transformer supplies a second DC output voltage that is regulated independently of the main DC output voltage. Two switching devices are used for each auxiliary DC output to regulate each auxiliary output voltage by adjusting the length of the on time of the pulses from the transformer's auxiliary secondary windings. Soft switching techniques are used to ensure that the switching devices turn on when the voltage across them is effectively zero.