Abstract: Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits.

Abstract: Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits.

Abstract: Apparatus for electrically coupling a first digital device (408) and a second digital device (406) includes an interface circuit at the first digital device coupled at an interface node (230) to the second digital device. The interface circuit is configured to provide a first device supply voltage (Vcc2) to the interface node until a second device supply voltage (Vcc) at the interface node exceeds the first voltage. A data circuit (220) at the first digital device is coupled to the interface node. The data circuit is responsive to voltage on the interface node for providing digital logic signals at appropriate voltage levels to the second digital device.

Abstract: A method and apparatus is described for the sequential display of status information on a mobile terminal by means of a rotating-icon. The operating condition of the mobile terminal is monitored and a plurality of status icons is selected and sequentially displayed for a predetermined time in substantially the same area of at least one screen such as a pixel screen. The predetermined time corresponds to M+(PV/S), where M is the minimum display time for each status icon, P is the priority allocated to a status icon about to be displayed in the at least one screen, S is the sum of all the priorities of the status icons in the selected plurality of status icons, and V=T−MN, where T is the total period of time allocated to sequentially display the selected plurality of status icons, and N is the number of status icons in the selected plurality of status icons.

Abstract: A system and method for updating software for a remote unit over a network is disclosed herein. The system and method includes the remote unit, an authentication server and an update server. The remote unit may have a flasher host for communicating over the network and for transmitting commands to the remote unit. The system and method allows for the verification of a request message from the remote unit, and a response from the authentication server. The response message to the remote unit from the authentication server will contain an decryption key to decrypt the update file that will be sent by the update server. Such an authentication process prevents rogue programs from being sent to the remote unit thereby decreasing the potential for cellular fraud.

Abstract: Apparatus for electrically coupling a first digital device (408) and a second digital device (406) includes an interface circuit at the first digital device coupled at an interface node (230) to the second digital device. The interface circuit is configured to provide a first device supply voltage (Vcc2) to the interface node until a second device supply voltage (Vcc) at the interface node exceeds the first voltage. A data circuit (220) at the first digital device is coupled to the interface node. The data circuit is responsive to voltage on the interface node for providing digital logic signals at appropriate voltage levels to the second digital device.

Abstract: A method and apparatus multiplexes pins of a PC card (104) to provide communication of two-way, high quality audio data between the PC card and a host computer (102) over a conventional PC card connector. The PC card includes one or more signal drivers (310), each signal driver coupled to a unidirectional signal line conventionally conveying address data from the host computer to the PC card. The signal drivers are configured to provide data signals to the signal line for communication to the host computer in an active mode and to enter a high impedance state in an inactive mode in response to a control signal received at a control input (314).

Abstract: Electromagnetic shielding devices are provided that can be easily modified in shape and configuration to facilitate electronic device development. An electronic substrate includes a surface and a ground trace extending along the surface to define a perimeter of an area of the electronic substrate to be shielded. A plurality of electrically conductive block members are electrically secured to the ground trace in adjacent relationship. An electrically conductive cover is electrically secured to a top face of each of the block members to overlie the area of the electronic surface to be shielded.

Abstract: Systems and methods of obtaining status information from PCMCIA cards installed within host computers are provided. A PCMCIA card includes a processor having a static random access memory (SRAM) attribute memory address space implemented therewithin. The SRAM attribute memory address space includes a Card Information Structure (CIS) that is readable by the host computer. Owner control signals provide an indication of ownership of the SRAM attribute memory address space. A host computer reads PCMCIA card status information from a CIS when an owner control signal indicates host computer ownership of the SRAM attribute memory address space. A host computer is prevented from reading status information from a CIS when an owner control signal indicates PCMCIA card processor ownership of a SRAM attribute memory address space.

Abstract: Apparatus for electrically coupling a first digital device (408) and a second digital device (406) includes an interface circuit at the first digital device coupled at an interface node (230) to the second digital device. The interface circuit is configured to provide a first device supply voltage (Vcc2) to the interface node until a second device supply voltage (Vcc) at the interface node exceeds the first voltage. A data circuit (220) at the first digital device is coupled to the interface node. The data circuit is responsive to voltage on the interface node for providing digital logic signals at appropriate voltage levels to the second digital device.

Abstract: Electromagnetic shielding devices are provided that can be easily modified in shape and configuration to facilitate electronic device development. An electronic substrate includes a surface and a ground trace extending along the surface to define a perimeter of an area of the electronic substrate to be shielded. A plurality of electrically conductive block members are electrically secured to the ground trace in adjacent relationship. An electrically conductive cover is electrically secured to a top face of each of the block members to overlie the area of the electronic surface to be shielded.

Abstract: A clock circuit includes a clock signal generator for generating a first clock signal during a normal mode of operation and an oscillating dual clock generating circuit for producing a second clock signal during a second mode of operation. The oscillating dual clock generating circuit is connected to the output of the clock signal generator. In the first mode of operation, the clock signal from the clock signal generator is passed through the oscillating dual clock generating circuit to a control device. In a second mode of operation, the input of the oscillating research signal is isolated. Isolation of the oscillating dual clock generating circuit causes oscillation in the dual clock generating circuit. Thus, the dual clock generating circuit acts as an oscillator during the second mode of operation to generate a second clock signal.

Abstract: Lockup in escaped mode for asynchronous paired modems on a communications link utilizing DTE echo back verification protocol is prevented by adding logic to each modem to detect and suppress transmission by the modem to its paired modem of at least one of any escape sequence characters received by a modem from its attached DTE. This prevents the unintentional placement of the paired modem, which would otherwise be transmitting echoed back characters from its DTE, from entering into the escape mode of operation due to what it would recognize as "escape sequence" characters received as "echo back" verification from its DTE.

Abstract: The invention permits multiple secondary stations to be connected in a multipoint communication network to a single primary station utilizing point-to-point interfaces such as the standard RS-232 or V.35 which do not ordinarily support multipoint connections. A primary station is connected to one secondary station or modem through a point-to-point interface utilizing either a straight through or cross over cable depending upon whether a modem is included. Data goes through the secondary station or modem to a second interface which is connected to a different secondary station or modem. This type of connection is referred to as a daisy chain. Data is not buffered in the secondary stations but is transmitted directly through each station. Each station monitors the daisy chain signals for clocking, status and identification of data for itself. Since there is no buffering, only a single set of clocking can be used in the chain.