Abstract: A differential negative resistance source that provides negative resistance to a differential resonator of a differential VCO. The differential negative resistance source includes first and second active devices, each having first and second current terminals and a control terminal, first and second current sinks, each coupled to a corresponding one of the second current terminals of the first and second active devices, and at least one capacitive device coupled between the second terminals of the first and second active devices. The capacitive device and the separate current sinks form a capacitive degeneration circuit that operates to reduce or otherwise eliminate net differential capacitance at the output of the differential negative resistance source. The capacitive degeneration offsets extra capacitance, which enables an increase of the maximum operating frequency for a given process, and which enables the VCO to be less sensitive to operating conditions.

Abstract: A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals.

Abstract: An automatic gain control (AGC) amplifier including a high gain transimpedance amplifier, a resistive feedback network and multiple transconductance stages coupled in the feedback path of the AGC amplifier. The feedback network receives an input signal and is coupled to the output of the high gain amplifier and has multiple intermediate nodes. Each transconductance stage has an input coupled to an intermediate node of the feedback network and an output coupled to the input of the high gain amplifier. Each transconductance stage is independently controllable to position a virtual ground within the feedback network to control closed loop gain. Each transconductance stage may have a bias current input coupled to a bias current control circuit. The control circuit controls each bias current to vary the gain of the AGC amplifier. The bias currents may be linearly controlled employing a ramp function to achieve a linear in dB gain response.

Abstract: A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency (ZIF) architecture. The device includes a ZIF transceiver and a baseband processor, which further includes a calibrator that periodically performs a calibration procedure. The baseband processor includes gain control logic, DC control logic, a gain converter and the calibrator. The gain converter converts gain between the gain control logic and the DC control logic. The calibrator programs the gain converter with values determined during the calibration procedure. The gain converter may be a lookup table that stores gain conversion values based on measured gain of a baseband gain amplifier of the ZIF transceiver. The gain control logic may further include a gain adjust limiter that limits change of a gain adjust signal during operation based on a maximum limit or on one or more gain change limits.

Abstract: A differential negative resistance source that provides negative resistance to a differential resonator of a differential VCO. The differential negative resistance source includes first and second active devices, each having first and second current terminals and a control terminal, first and second current sinks, each coupled to a corresponding one of the second current terminals of the first and second active devices, and at least one capacitive device coupled between the second terminals of the first and second active devices. The capacitive device and the separate current sinks form a capacitive degeneration circuit that operates to reduce or otherwise eliminate net differential capacitance at the output of the differential negative resistance source. The capacitive degeneration offsets extra capacitance, which enables an increase of the maximum operating frequency for a given process, and which enables the VCO to be less sensitive to operating conditions.

Abstract: A phase error detector that detects phase error between differential signals. A quadrature oscillator provides in-phase (I) and quadrature phase (Q) differential carrier signals and receives a phase error signal from the phase error detector. The oscillator maintains a quarter cycle phase delay between the I and Q carrier signals based on the phase error signal. The phase error detector includes a summing network and first and second bipolar transistor mixer circuits. The summing network develops four sum signals by summing respective pairs of the differential components of the I and Q carrier signals. A bias circuit biases the transistors to turn on at positive base voltages. The mixer circuits may include filter capacitors so that the transistors are responsive to positive base voltages. The mixer circuits develop polarity signals based on the sum signals, and the resulting phase error signal is the differential of the polarity signals.

Abstract: An attenuator control circuit for controlling operation of a differential pair attenuator to provide linear in decibels (dB) operation and temperature and process-independent operation. The attenuator control circuit is coupled in parallel with corresponding control input terminals of the attenuator differential pair. The attenuator control circuit also includes a current control circuit that sources a supply current to the control differential pair. The attenuator control circuit also includes an amplifier that controls current through the first current path of the control differential pair to maintain constant total current, so that the first current path exhibits the desired exponential attenuation function. Since the control differential pair is coupled in parallel with the differential pair attenuator, the output current of the differential pair attenuator also exhibits the desired exponential attenuation function.

Abstract: A variable transconductance amplifier including a variable attenuator stage coupled to a transconductance stage. The variable attenuator includes first and second differential to single-ended transconductance stages, each biased by a current device. The variable attenuator receives a differential input voltage signal and develops a current signal. At least one reactive element is coupled between the pair of differential to single-ended transconductance stages. The transconductance stage includes first and second differential pairs each having first and second control terminals and first and second output terminals. The first and second differential pairs are coupled to the first and second differential to single-ended transconductance stages, respectively, of the variable attenuator. The output terminals of the first and second differential pair are cross-coupled to develop a differential output current signal.

Abstract: A wireless communication device including a radio frequency (RF) circuit, a ZIF transceiver and a baseband processor. The ZIF transceiver includes an RF mixer circuit that converts the RF signal to a baseband input signal, a summing junction that subtracts a DC offset from the baseband input signal to provide an adjusted baseband input signal, and a baseband amplifier that receives the adjusted baseband input signal and that asserts an amplified input signal based on a gain adjust signal. The baseband processor includes gain control logic, DC control logic and a gain interface. The gain control logic receives the amplified input signal, estimates input signal power and asserts the gain adjust signal in an attempt to keep the input signal power at a target power level. The DC control logic estimates an amount of DC in the amplified input signal and provides the DC offset in an attempt to reduce DC in the amplified input signal.

Abstract: A variable transconductance amplifier including a variable attenuator stage coupled to a transconductance stage. The variable attenuator includes first and second differential to single-ended transconductance stages, each biased by a current device. The variable attenuator receives a differential input voltage signal and develops a current signal. At least one reactive element is coupled between the pair of differential to single-ended transconductance stages. The transconductance stage includes first and second differential pairs each having first and second control terminals and first and second output terminals. The first and second differential pairs are coupled to the first and second differential to single-ended transconductance stages, respectively, of the variable attenuator. The output terminals of the first and second differential pair are cross-coupled to develop a differential output current signal.

Abstract: An automatic gain control (AGC) circuit including a high gain amplifier, a feedback network and two transconductance amplifiers. The feedback network has a first end that receives an input signal of the AGC circuit, a second end coupled to the output of the high gain amplifier and two intermediate nodes. Each transconductance amplifier has an input coupled to a respective intermediate node of the feedback network and an output coupled to the input of the high gain amplifier. The transconductance amplifiers collectively control a position of a virtual ground within the feedback network to control gain of the AGC circuit. The transconductance amplifiers each include an attenuator and a transconductance stage coupled between the feedback network and the high gain amplifier and are configured to operate linearly across a relatively wide input voltage range. The input offset voltage of the AGC circuit varies monotonically with gain of the AGC circuit.

Abstract: An amplifier with common mode output control including a reference circuit, a current mirror input circuit, a differential current mirror, a summing junction, first and second feedback amplifiers, first and second feedback current mirrors, and a differential output circuit. The input circuit receives the differential input voltage and develops a differential input current having polarity currents that have a constant sum based on a reference signal. The differential current mirror mirrors the differential input current into first and second high impedance nodes. The feedback amplifiers and the feedback current mirrors generate feedback current into the high impedance nodes in response to variations of summing junction voltage and maintain a constant common mode current. The output circuit develops a differential output current based on the differential input current mirrored into the high impedance nodes. RC compensation is provided to compensate open loop gain and the common mode output current loop.

Abstract: A mixer driver circuit including a differential pair, a differential current supply and a switched current sink. The differential pair has a differential input for receiving a differential input signal. The differential current supply provides a differential output and switches in response to switching of the differential pair to provide a differential output current. The switched current sink biases the differential current supply and sinks current to drive the differential output signal. The differential pair may be a resistive-loaded differential pair of transistors biased by a constant current sink. The differential current supply may include a pair of emitter follower buffers. The mixer driver may further include a pair of constant current sinks and a second pair of emitter follower buffers, where the second pair of emitter follower buffers is biased by the pair of constant current sinks and provides a voltage level shifting drive for the switched current sink.

Abstract: An automatic gain control (AGC) circuit including a high gain amplifier, a feedback network and two transconductance amplifiers. The feedback network has a first end that receives an input signal of the AGC circuit, a second end coupled to the output of the high gain amplifier and two intermediate nodes. Each transconductance amplifier has an input coupled to a respective intermediate node of the feedback network and an output coupled to the input of the high gain amplifier. The transconductance amplifiers collectively control a position of a virtual ground within the feedback network to control gain of the AGC circuit. The transconductance amplifiers each include an attenuator and a transconductance stage coupled between the feedback network and the high gain amplifier and are configured to operate linearly across a relatively wide input voltage range. The input offset voltage of the AGC circuit varies monotonically with gain of the AGC circuit.

Abstract: A linearization bias circuit for an RF BJT amplifier including a reference circuit, a current device and a transconductance amplifier. The linearization bias circuit controls the operating point of the BJT amplifier based on signal level of an input RF signal. The current device provides a constant reference current to the reference circuit, where the constant reference current has a level that is based on a desired collector current of the BJT amplifier. The reference circuit applies a predetermined relationship between DC and AC scale factors of collector current of the BJT amplifier. The transconductance amplifier asserts its output to maintain the constant reference current into the reference terminal of the reference circuit, and in doing so controls the base terminal of the BJT amplifier to modify its operating point to substantially maintain constant transconductance in the presence of varying input voltage amplitudes of the input RF signal.

Abstract: An automatic gain control (AGC) amplifier including a high gain transimpedance amplifier, a resistive feedback network and multiple transconductance stages coupled in the feedback path of the AGC amplifier. The feedback network receives an input signal and is coupled to the output of the high gain amplifier and has multiple intermediate nodes. Each transconductance stage has an input coupled to an intermediate node of the feedback network and an output coupled to the input of the high gain amplifier. Each transconductance stage is independently controllable to position a virtual ground within the feedback network to control closed loop gain. Each transconductance stage may have a bias current input coupled to a bias current control circuit. The control circuit controls each bias current to vary the gain of the AGC amplifier. The bias currents may be linearly controlled employing a ramp function to achieve a linear in dB gain response.

Abstract: An amplifier with common mode output control including a reference circuit, a current mirror input circuit, a differential current mirror, a summing junction, first and second feedback amplifiers, first and second feedback current mirrors, and a differential output circuit. The input circuit receives the differential input voltage and develops a differential input current having polarity currents that have a constant sum based on a reference signal. The differential current mirror mirrors the differential input current into first and second high impedance nodes. The feedback amplifiers and the feedback current mirrors generate feedback current into the high impedance nodes in response to variations of summing junction voltage and maintain a constant common mode current. The output circuit develops a differential output current based on the differential input current mirrored into the high impedance nodes. RC compensation is provided to compensate open loop gain and the common mode output current loop.

Abstract: A mixer driver circuit including a differential pair, a differential current supply and a switched current sink. The differential pair has a differential input for receiving a differential input signal. The differential current supply provides a differential output and switches in response to switching of the differential pair to provide a differential output current. The switched current sink biases the differential current supply and sinks current to drive the differential output signal. The differential pair may be a resistive-loaded differential pair of transistors biased by a constant current sink. The differential current supply may include a pair of emitter follower buffers. The mixer driver may further include a pair of constant current sinks and a second pair of emitter follower buffers, where the second pair of emitter follower buffers is biased by the pair of constant current sinks and provides a voltage level shifting drive for the switched current sink.

Abstract: An attenuator control circuit for controlling operation of a differential pair attenuator to provide linear in decibels (dB) operation and temperature and process-independent operation. The attenuator control circuit is coupled in parallel with corresponding control input terminals of the attenuator differential pair. The attenuator control circuit also includes a current control circuit that sources a supply current to the control differential pair. The attenuator control circuit also includes an amplifier that controls current through the first current path of the control differential pair to maintain constant total current, so that the first current path exhibits the desired exponential attenuation function. Since the control differential pair is coupled in parallel with the differential pair attenuator, the output current of the differential pair attenuator also exhibits the desired exponential attenuation function.

Abstract: A phase error detector that detects phase error between differential signals. A quadrature oscillator provides in-phase (I) and quadrature phase (Q) differential carrier signals and receives a phase error signal from the phase error detector. The oscillator maintains a quarter cycle phase delay between the I and Q carrier signals based on the phase error signal. The phase error detector includes a summing network and first and second bipolar transistor mixer circuits. The summing network develops four sum signals by summing respective pairs of the differential components of the I and Q carrier signals. A bias circuit biases the transistors to turn on at positive base voltages. The mixer circuits may include filter capacitors so that the transistors are responsive to positive base voltages. The mixer circuits develop polarity signals based on the sum signals, and the resulting phase error signal is the differential of the polarity signals.