Patents by Inventor John Salazar

John Salazar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12160626
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to automate the recording of media for signature creation. Reference signature requests are received from an employee or user. The reference signature request is distributed to automated capture tool circuitry, which plays the relevant media for a meter and provides a status update. When a signature is created, a status update indicates whether it is considered to be a reference signature. Prioritization circuitry assigns and updates a priority for each of the requests according to the priority of other requests, the status updates, and a priority rule set. Reference signature requests with the highest priority are assigned to automated capture tool circuitry for completion before lower priority requests.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: December 3, 2024
    Assignee: The Nielsen Company (US), LLC
    Inventors: Albert T. Borawski, Shailendra Paranjape, Nigel Smith, Eric M. Rosell, John Ferrell, Jessica Salazar, Morgan Nibert, David Christie
  • Patent number: 10714413
    Abstract: The present disclosure relates to a lead frame assembly for a semiconductor device. The leadframe assembly includes a clip frame structure with a die connection portion configured and arranged for contacting to one or more contact terminals on a top side of a semiconductor die; and one or more electrical leads extending from the die connection portion at a first end. The die connection portion includes a hooking tab extending therefrom configured and arranged to engage with a wire loop of a wire pull test equipment. The disclosure also relates to an interconnected matrix of such leadframe.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 14, 2020
    Assignee: Nexperia B.V.
    Inventors: Ricardo Lagmay Yandoc, Adam Richard Brown, Reinald John Salazar Roscain
  • Publication number: 20200194354
    Abstract: The present disclosure relates to a lead frame assembly for a semiconductor device. The leadframe assembly includes a clip frame structure with a die connection portion configured and arranged for contacting to one or more contact terminals on a top side of a semiconductor die; and one or more electrical leads extending from the die connection portion at a first end. The die connection portion includes a hooking tab extending therefrom configured and arranged to engage with a wire loop of a wire pull test equipment. The disclosure also relates to an interconnected matrix of such leadframe.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 18, 2020
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Lagmay YANDOC, Adam Richard BROWN, Reinald John Salazar ROSCAIN
  • Publication number: 20090013660
    Abstract: A system for improving maneuverability and safety of a clutch driven landscaping utility vehicle has a set of vehicle track belts comprising of one track belt per set of front and rear wheels, a tension adjuster for controlling tension of the track belts over the wheels, and a track guard for preventing debris from dislodging the track belt during operation.
    Type: Application
    Filed: July 14, 2008
    Publication date: January 15, 2009
    Inventor: John Salazar
  • Publication number: 20070210819
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 13, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205756
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205773
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205797
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205757
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205786
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205796
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20070205758
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: May 10, 2007
    Publication date: September 6, 2007
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20060152237
    Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.
    Type: Application
    Filed: January 12, 2005
    Publication date: July 13, 2006
    Inventors: John Corbin, Jose Garza, Dales Kent, Kenneth Larsen, Howard Mahaney, Hoa Phan, John Salazar
  • Publication number: 20050040838
    Abstract: A chip testing system with improved thermal performance. In a preferred embodiment, a nest assembly of a chip testing apparatus includes tooling balls and a fitted frame for improving alignment of a coldplate and a chip surface. In preferred embodiments, the coldplate is of unibody design. Thermal performance is also improved by balancing the forces exerted on the coldplate using an adjustable hose mounting bracket. The bracket allows the forces exerted by the hoses on the coldplate to be adjusted so they balance and cancel other unwanted forces on the cold plate.
    Type: Application
    Filed: August 21, 2003
    Publication date: February 24, 2005
    Applicant: International Business Machines Corporation
    Inventors: Lonnie Cannon, John Corbin, David Gardell, Jose Garza, Jeffrey Kutner, Kenneth Larsen, Howard Mahaney, John Salazar
  • Patent number: 4936619
    Abstract: A hand grip for carrying one or more plastic bags or the like which includes an elongate tubular element having a hollow interior and a pair of spaced apart panels. The panels are affixed to the tubular element and diverge outwardly therefrom defining a channel therebetween which communicates with the interior of the tubular element through an opening dimensioned to provide some resistance to passage therethrough of a bag handle.
    Type: Grant
    Filed: May 12, 1989
    Date of Patent: June 26, 1990
    Inventor: John Salazar