Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A structure and method of using the structure. The structure including an integrated circuit chip having a set of micro-channels; an electro-rheological coolant fluid filling the micro-channels; first and second parallel channel electrodes on opposite sides of at least one micro-channel, the first channel electrode connected to an output of an auto-compensating temperature control circuit, the second channel electrode connected to ground; the auto-compensating temperature control circuit comprising a temperature stable current source connected between a positive voltage rail and the output and having a temperature sensitive circuit connected between ground and the output, a leakage current of the temperature stable current source being essentially insensitive to temperature and a leakage current of the temperature sensitive circuit increasing with temperature.

Abstract: A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.

Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

Abstract: A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Abstract: A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Abstract: A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Abstract: A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Abstract: A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals to simulations of the critical paths and monitors the number of times each of the functional test signals propagate from the beginning to the end of each of the critical paths. This allows the method to identify stress producing test signals as those that propagate along the critical paths more than other test signals. These stress producing test signals are applied to integrated circuit chip hardware manufactured according to the integrated circuit chip design to stress test the hardware.

Abstract: For testing a logic unit under test (UUT), rule-based random irritation of a UUT model is provided to be used in conjunction with a simulator. The UUT model is stimulated (or irritated) with data patterns randomly generated by a pattern generator within the boundary of limitations imposed by a rules list. The rules list provides restrictions or encouragements on how data patterns are to be applied to the software model of the UUT. The pattern generator may be implemented either within or outside the simulator. If the pattern generator is incorporated into the simulator, then a software environment is required to interface communications between the pattern generator, the simulator, and other software entities involved in the simulation.

Abstract: For testing a logic unit under test (UUT), rule-based random irritation of a UUT model is provided to be used in conjunction with a simulator. The UUT model is stimulated (or irritated) with data patterns randomly generated by a pattern generator within the boundary of limitations imposed by a rules list. The rules list provides restrictions or encouragements on how data patterns are to be applied to the software model of the UUT. The pattern generator may be implemented either within or outside the simulator. If the pattern generator is incorporated into the simulator, then a software environment is required to interface communications between the pattern generator, the simulator, and other software entities involved in the simulation.