Abstract: A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.

Abstract: A signal detector circuit and digital signal receiver implementing the same. In one embodiment the digital signal receiver includes a switch point detector having a detector output and including a transistor array comprising one or more pull-up branches and one or more pull-down branches. A switch point control circuit is coupled to the switch point detector. The switch point control circuit generates branch enable signals for selectively enabling or disabling said one or more pull-up branches and said one or more pull-down branches in a detector output polarity dependent manner.