Abstract: A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing.

Abstract: A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested.

Abstract: A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.