Abstract: A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.

Abstract: A combiner system for frequency combining and related methods. Implementations may include a plurality of combiner stages each including a deinterleaver, at least one filter, a frequency downconverter, and a frequency upconverter all operatively coupled together. Each of the plurality of combiner stages may be adapted to receive a complex interleaved input signal including two or more input signals each including a bandwidth, to output a complex stage output signal including the two or more input signals, and to alternately place the bandwidth of each of the two or more input signals in an upper portion and in a lower portion of an output bandwidth of the complex stage output signal. The upper portion and lower portion of the output bandwidth may be contiguous within the output bandwidth and joined at a center of the output bandwidth.

Abstract: A burst processing modem and related methods. Implementations of a first method of demodulating bursts from a plurality of channels may include receiving a plurality of channels from a received beam and separating the plurality of channels and storing a plurality of frames in a random access memory (RAM) array with a channelizer where each frame of the plurality of frames includes one or more bursts. The method may include serially reading, using a demodulator in response to receiving a timing signal, a desired burst from a frame stored in the RAM array wherein a burst time plan identifying the desired burst is used by a receive frame state machine to generate the timing signal. The method may include demodulating and decoding the desired burst using a demodulator and a decoder to produce a quantity of packet data, and sending the quantity of packet data to a specified destination.

Abstract: A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.

Abstract: A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.

Abstract: A burst processing modem and related methods. Implementations of a first method of demodulating bursts from a plurality of channels may include receiving a plurality of channels from a received beam and separating the plurality of channels and storing a plurality of frames in a random access memory (RAM) array with a channelizer where each frame of the plurality of frames includes one or more bursts. The method may include serially reading, using a demodulator in response to receiving a timing signal, a desired burst from a frame stored in the RAM array wherein a burst time plan identifying the desired burst is used by a receive frame state machine to generate the timing signal. The method may include demodulating and decoding the desired burst using a demodulator and a decoder to produce a quantity of packet data, and sending the quantity of packet data to a specified destination.

Abstract: A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.

Abstract: A combiner system for frequency combining and related methods. Implementations may include a plurality of combiner stages each including a deinterleaver, at least one filter, a frequency downconverter, and a frequency upconverter all operatively coupled together. Each of the plurality of combiner stages may be adapted to receive a complex interleaved input signal including two or more input signals each including a bandwidth, to output a complex stage output signal including the two or more input signals, and to alternately place the bandwidth of each of the two or more input signals in an upper portion and in a lower portion of an output bandwidth of the complex stage output signal. The upper portion and lower portion of the output bandwidth may be contiguous within the output bandwidth and joined at a center of the output bandwidth.