Abstract: A method for analyzing an integrated circuit (IC). At least a portion of a layer of the IC is scanned using high magnification, to obtain images of the IC. The images are registered to create a mosaicked image. An IC layout database is created in the form of a set of polygons from the mosaicked image, where the step of creating the IC layout database is performed after, or pipelined with, the registering step. The process is repeated for plural IC layers, as necessary. Polygon sets from each layer are vertically registered into alignment with minimal distortion. A netlist or schematic diagram is generated to represent the scanned IC portion based on the registered set(s) of polygons.