Patents by Inventor John Sharkey

John Sharkey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941296
    Abstract: Intelligent storage of messages is provided. A spill-over page set is selected to store received messages corresponding to a predefined target page set associated with an application workload in response to the predefined target page set reaching a predefined minimum unused page threshold level. The spill-over page set is utilized as a message storage destination for the received messages corresponding to the predefined target page set associated with the application workload to extend message storage for the predefined target page set after the predefined target page set reached the predefined minimum unused page threshold level.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Juan Zhang, Anthony John Sharkey
  • Publication number: 20230214156
    Abstract: Intelligent storage of messages is provided. A spill-over page set is selected to store received messages corresponding to a predefined target page set associated with an application workload in response to the predefined target page set reaching a predefined minimum unused page threshold level. The spill-over page set is utilized as a message storage destination for the received messages corresponding to the predefined target page set associated with the application workload to extend message storage for the predefined target page set after the predefined target page set reached the predefined minimum unused page threshold level.
    Type: Application
    Filed: January 3, 2022
    Publication date: July 6, 2023
    Inventors: Juan Zhang, Anthony John Sharkey
  • Publication number: 20070084974
    Abstract: Apparatus, methods and a communication system for providing relatively constant warning time at a rail grade crossing for trains with prediction of the approach of a train from a remote controller via rail-based communications to a crossing controller. A first communication signal is generated when a prediction occurs and a second communication signal is generated for slower moving trains, with the second signal temporarily overriding the first signal to provide relatively constant warning time at the crossing. Cancellation timers with timing intervals are used to resolve situations where the train does not enter the approach or where the train leaves by way of a switch or backs out. Directional logic is used to determine the direction of movement of the train and, in conjunction with cancellation timers, causes the warning devices to be activated when the timers expire.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 19, 2007
    Inventors: John Sharkey, Richard Bamfield, Martin Paget
  • Publication number: 20060287353
    Abstract: Macrolide compound, such as a tacrolimus analogue is provided for use as a neuroprotective agent, particularly, for preventing or treating acute or chronic cerebral neurodegenerative diseases.
    Type: Application
    Filed: April 18, 2006
    Publication date: December 21, 2006
    Applicant: Astellas Pharma Inc.
    Inventors: Paul Jones, John Sharkey, John Kelly
  • Publication number: 20060261219
    Abstract: An electronic controller for a highway-railroad grade crossing warning system is coupled to an approach circuit and to an island circuit and activates a warning device when a train is present in either of the approach or the island circuits. The controller has a display with touch-sensitive fields for selectively taking the approach circuit or island circuit out of service. Additional touch-sensitive fields on the display may be used for selecting the amount of time that the approach or island circuits remain out of service and for confirming that the maintainer wishes to take the these circuits out of service. Service is automatically restored upon expiration of the selected amount of time.
    Type: Application
    Filed: May 18, 2005
    Publication date: November 23, 2006
    Inventors: John Sharkey, Richard Bamfield
  • Publication number: 20040201486
    Abstract: A solid state crossing controller for a railroad crossing signal system with two independent outputs for controlling illumination of lamps in the signal system share a common neutral or return wire, with sensing of a common neutral or return line shared by the two independent outputs to determine any loss of the neutral line. When a failure has been detected in the neutral line, the controller modifies the voltages for the lamps in the signaling system for better illumination of the lamps during the failure condition, such as to the highest voltage available from a battery in the system. Upon detection of the failure in the neutral line, the controller may provide a call or message that there is a failure in the system that is in need of repair. If the failure in the neutral line is intermittent, the controller will resume normal operation after that train, has cleared the crossing. However, a call or message that a failure has occurred in the neutral line is provided.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 14, 2004
    Inventors: Thomas Knowles, Rakesh Malhotra, Hung Pham, John Sharkey
  • Publication number: 20040092528
    Abstract: The present invention relates to an agent for modulating excitatory synaptic transmission which contains a compound having &agr;7 nicotinic acetylcholine receptor activation property as an active ingredient, and the production of such an agent. It further relates to a pharmaceutical composition which contains such a compound together with a pharmaceutically acceptable carrier or excipient, and a method for modulating excitatory synaptic transmission which comprises administering such a composition. There is also provided a method for screening an agent for modulating excitatory synaptic transmission which comprises using &agr;7 nicotinic acetylcholine receptor activation property as an index. The present invention is useful for the prophylaxis and/or treatment of cerebral diseases, including dementia, amnesia, manic-depressive psychosis, schizophrenia, Parkinson's disease and psychosomatic disease.
    Type: Application
    Filed: July 22, 2003
    Publication date: May 13, 2004
    Inventors: John S Kelly, Joseph Hodgkiss, John Sharkey
  • Patent number: 5648351
    Abstract: The present invention relates to a new use of macrolide compounds of the formula (I): ##STR1## wherein each symbol is as defined in the specification, for preventing or treating cerebral ischemic disease, such as, brain damage caused by ischemia, such as cerebral infarction. So, they are useful when the following diseases or injury occur. That is, head injury, hemorrhage in brain such as subarachnoid hemorrhage or intracerebral hemorrhage, cerebral thrombosis, cerebral embolism, cardiac arrest, stroke, transient ischemic attacks (TIA), hypertensive encephalopathy and so on.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: July 15, 1997
    Assignee: Fujisawa Pharmaceutical Co., Ltd.
    Inventors: John S. Kelly, Steven P. Butcher, John Sharkey
  • Patent number: 5185859
    Abstract: A graphics processor device performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: February 9, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Karl M. Guttag, Michael Asal, Richard Simpson, Thomas Preston, John Sharkey
  • Patent number: 5056041
    Abstract: A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: October 8, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Karl M. Guttag, Michael Asal, Richard Simpson, Thomas Preston, John Sharkey