Abstract: The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete "dotted " segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.

Abstract: The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete "dotted" segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.