Patents by Inventor John Shigeto Minami

John Shigeto Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040213290
    Abstract: An Internet network protocol stack, along with special logic, is embedded with a modem, thereby enabling a modem to become Internet-ready. As a result, the modem offloads much of the network protocol processing from the main CPU and improves the overall performance of the communication system.
    Type: Application
    Filed: May 20, 2004
    Publication date: October 28, 2004
    Inventors: Michael Ward Johnson, John Shigeto Minami, Ryo Koyama
  • Patent number: 6765901
    Abstract: An Internet network protocol stack, along with special logic, is embedded with a modem, thereby enabling a modem to become Internet-ready. As a result, the modem offloads much of the network protocol processing from the main CPU and improves the overall performance of the communication system.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: July 20, 2004
    Assignee: NVIDIA Corporation
    Inventors: Michael Ward Johnson, John Shigeto Minami, Ryo Koyama
  • Publication number: 20040062267
    Abstract: The invention is embodied in a gigabit Ethernet adapter. A system according to the invention provides a compact hardware solution to handling high network communication speeds. In addition, the invention adapts to multiple communication protocols via a modular construction and design.
    Type: Application
    Filed: June 5, 2003
    Publication date: April 1, 2004
    Inventors: John Shigeto Minami, Robin Yasu Uyeshiro, Michael Ward Johnson, Steve Su, Michael John Sebastian Smith, Addison Kwuanming Chen, Mihir Shaileshbhai Doctor, Daniel Leo Greenfield
  • Publication number: 20030165160
    Abstract: A gigabit Ethernet adapter provides a provides a low-cost, low-power, easily manufacturable, small form-factor network access module which has a low memory demand and provides a highly efficient protocol decode. The invention comprises a hardware-integrated system that both decodes multiple network protocols in a byte-streaming manner concurrently and processes packet data in one pass, thereby reducing system memory and form factor requirements, while also eliminating software CPU overhead. A preferred embodiment of the invention comprises a plurality of protocol state machines that decode network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, Raw Socket, RARP, ICMP, IGMP, iSCSI, RDMA, and FCIP concurrently as each byte is received. Each protocol handler parses, interprets, and strips header information immediately from the packet, requiring no intermediate memory. The invention provides an Internet tuner core, peripherals, and external interfaces.
    Type: Application
    Filed: April 23, 2002
    Publication date: September 4, 2003
    Inventors: John Shigeto Minami, Robin Yasu Uyeshiro, Michael Ward Johnson, Steve Su
  • Publication number: 20020078115
    Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET, and Java.IO application frameworks are supported in the preferred embodiment of the invention. Application framework classes are stored as libraries in a shared memory. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit. Additional application frameworks can be supported by modifying or replacing the software stub. Hardware object management system requests are executed by an application framework-specific hardware accelerator.
    Type: Application
    Filed: June 20, 2001
    Publication date: June 20, 2002
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Patent number: 6330659
    Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET, and Java.IO application frameworks are supported in the preferred embodiment of the invention. Application framework classes are stored as libraries in a shared memory. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit. Central processing unit processing of non-supported application framework instructions is continued during hardware accelerator execution of hardware object management system requests.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 11, 2001
    Assignee: iReady Corporation
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Patent number: 6034963
    Abstract: A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML).
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: March 7, 2000
    Assignee: iReady Corporation
    Inventors: John Shigeto Minami, Ryo Koyama, Michael Ward Johnson, Masaru Shinohara, Thomas C. Poff, Daniel F. Burkes