Patents by Inventor John Shurboff

John Shurboff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5525204
    Abstract: Fabricating a printed circuit by forming layers of metallization in a predetermined sequence, where each layer is formed in a predetermined pattern, with a layer of plating formed at selected locations of the printed circuit. Subsequently, forming a layer of insulation over the layers of metallization, except at the selected locations.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: June 11, 1996
    Assignee: Motorola, Inc.
    Inventors: John Shurboff, Ang L. Eng
  • Patent number: 4700473
    Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.
    Type: Grant
    Filed: September 2, 1986
    Date of Patent: October 20, 1987
    Assignee: Motorola Inc.
    Inventors: Bruce J. Freyman, Dale Dorinski, John Shurboff
  • Patent number: 4700276
    Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.
    Type: Grant
    Filed: January 3, 1986
    Date of Patent: October 13, 1987
    Assignee: Motorola Inc.
    Inventors: Bruce J. Freyman, Dale Dorinski, John Shurboff