Abstract: A forward projector/backprojector (30) for a CT scanner (10) includes a VME interface (36) which loads data onto and off of the forward projector/backprojector (30), and a CPU (42) which controls data flow. An array of ASICs (60a-x) is included. Each ASIC has two pipelines along which data is subjected to pipeline operations including one of a forward projection algorithm and a backprojection algorithm. Double-buffered memories for storing data subject to the pipeline operations are arranged on each ASIC (60a-x) such that while data is loaded into one bank of the double-buffered memories data in its opposing bank is subject to pipeline operations. A dual in-line memory module (DIMM) daughtercard (120) holds an output memory (100) with two banks employed during pipeline operations.

Abstract: A customized random access memory circuit is provided to allow the processing of extremely high amounts of data in an area of very small physical size. The chip contains a group of interconnected registers with a set of input ports and a set of output ports. The input ports have individual write enable signals to allow them to write to selected address locations. A switching circuit is provided to ensure that the proper data from the proper input port goes to the chosen address location. A first and second set of latches are provided where the first set of latches are connected to a multiplexor first and the second set of latches are connected to a second multiplexor. The chip also contains a cycle skipping chip to allow the data to maintain its position and not be transferred through at least one clock cycle. Selected data sets which are going to be outputted have the data internally swapped to prepare it for use in floating point operations.

Abstract: An array processor has been designed in a highly paralleled fashion thereby allowing extremely fast movement of data. Two 32-bit words come out of an internal data memory device. This data is fed into a register file. On the same clock cycle, three 32-bit results are coming out of an arithmetic unit. Those results feed back into the register file. Therefore, on a single clock cycle, five separate pieces of data are going into the register file. In the same clock cycle, other data coming out of the outputs of the register file feed data into two separate floating arithmetic adders and one floating arithmetic multiplier. The design of the present embodiment allows a constant flow of data to be supplied to the arithmetic unit thereby using the arithmetic unit to its maximum functioning ability.