Patents by Inventor John Silver

John Silver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating gate reference for sleep/hibernate regulator
    Patent number: 8339188
    Abstract: A system includes power saving circuitry to revive a system controller from a sleep mode for performance of operations in an active mode. The system also includes a regulator including a floating gate reference device to generate output voltage and current capable of powering the power saving circuitry during the sleep mode. A method includes generating a reference voltage and current with a float gate device, and powering wake-up circuitry with the reference voltage and current while in a power saving mode. The wake-up circuitry is configured to activate a main system controller from the power saving mode.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: December 25, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: John Silver, Harold Kutz, Gary Moscaluk
  • Method and circuit for high speed transmission gate logic
    Patent number: 7053662
    Abstract: A transmission gate logic circuit (200) can include a supply path (206) connected to an output of a passgate (202). A boost path (208) can be situated between an input of passgate (202) and the supply path (206) and can enable a first supply device (206-0) within the supply path (206) in response to a signal C at the input of passgate (202). A supply path (208) can thus provide a boost at the output node (214) of passgate (202) resulting in faster logic transition times.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 30, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: John Silver, Bogdan Georgescu
  • Architecture, circuitry and method of transferring data into and/or out of an interdigitated memory array
    Patent number: 6629185
    Abstract: An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: September 30, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: John Silver, Iulian Gradinariu, Keith Ford, Sean Mulholland
  • SRAM memory cell
    Patent number: 5166902
    Abstract: A compact SRAM memory cell employs two invertor areas longitudinally offset along a longitudinal axis and having transistor gates interdigitated, with a gate electrode of one invertor extending perpendicular to the longitudinal axis to make contact with the output node of the other invertor. Adjacent cells are related by a 180.degree. rotation through a transverse edge and a reflection through a longitudinal edge.
    Type: Grant
    Filed: March 18, 1991
    Date of Patent: November 24, 1992
    Assignee: United Technologies Corporation
    Inventor: John Silver
  • Preimplanted N-channel SOI mesa
    Patent number: 5104818
    Abstract: A silicon on insulator circuit having transistors formed in isolated mesas initially doped P.sup.-- has the mesas for N-channel transistors counterdoped to a N.sup.-- concentration, after which a field insulating layer is put down over an outer portion of the N-channel mesas and N-channel transistors with N.sup.+ sources and drains are formed, so that the N.sup.+ areas are adjacent the counterdoped N.sup.-- areas, thereby eliminating P-N junction found in prior art devices.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: April 14, 1992
    Assignee: United Technologies Corporation
    Inventor: John Silver