Abstract: The present disclosure is directed to a multi-segment device, such as an intravascular guide wire. The multi-segment device includes an elongate first portion comprising a first metallic material, an elongate second portion comprising a different metallic material, the first and second elongate portions being directly joined together end to end by a solid-state weld, and a heat affected zone surrounding an interface of the weld where the first and second portions are joined together, wherein the heat affected zone has an average thickness of less than about 0.20 mm.

Abstract: A toy assembly comprising a first section and a second section coupled to the first section. The first section includes a plurality of first section members positioned on an inner side of the first section. The second section includes a plurality of second section members positioned on an inner side of the second section. The plurality of second section members are heat welded directly to the plurality of first section members without any additional welding or filler material. The first section and the second section are solely held together by the heat welded first section members and second section members.

Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.

Abstract: The present disclosure relates to nanochannel plates for use in reverse osmosis systems and methods of their manufacture. An example nanochannel plate includes a first surface and an opposing second surface. The first surface and the second surface are parallel to a major flat of the nanochannel plate. The nanochannel plate also includes a plurality of channels. At least one channel includes a carbon nanotube having a first end opening proximate to the first surface and a second end opening proximate to the second surface. Optionally, a core portion of the carbon nanotube could be configured to transport water from the first surface to the second surface or vice versa. Optionally, the core portion of the carbon nanotube has a core diameter of less than or equal to 0.7 nanometers.

Abstract: An article of manufacture includes a support structure including a cladding material and defining therein a plurality of substantially parallel cores. The article also includes a plurality of conically-shaped spikes protruding from a first side of the support structure. Each respective conically-shaped spike of the plurality of conically-shaped spikes includes a core material (i) extending through a corresponding core of the plurality of substantially parallel cores and (ii) comprising an axial protrusion that protrudes axially from the cladding material at the first side of the support structure. The axial protrusion of the core material is tapered to form the respective conically-shaped spike. The article also includes a refractory metal layer coating at least a portion of each respective conically-shaped spike and one or more electrodes connected to the refractory metal layer and configured to apply a voltage to the refractory metal layer.

Abstract: A stent having a cobalt-based alloy, wherein the cobalt-based alloy is free of nickel (Ni), the cobalt-based alloy including 10-65 weight % metal member selected from a platinum group metal, a refractory metal, or combinations thereof, 15-25 weight % chromium (Cr), 4-7 weight % molybdenum (Mo), 0-18 weight % iron (Fe), and 22-40 weight % cobalt (Co).

Abstract: An apparatus includes a support structure defining therein substantially parallel cavities extending from a first side of the support structure to a second side of the support structure. The apparatus also includes optical fiber cores each extending from the second side through a corresponding cavity and protruding axially at the first side. The axial protrusion tapers from a first diameter down to a second diameter. The apparatus additionally includes a light emitter optically connected to the optical fiber cores and configured to emit light thereinto. A cut-off size associated with the light is greater than or equal to the second diameter such that an evanescent electromagnetic wave is generated at the cut-off portion. The apparatus further includes light detectors each being optically connected at the second side to a corresponding optical fiber core and configured to measure an intensity of the light reflected from the cut-off portion.

Abstract: Embodiments are directed to radiopaque implantable structures (e.g., stents) formed of cobalt-based alloys that comprise cobalt, chromium, tungsten, and nickel. Tungsten is present above its solubility limit (about 15%), but is still only present as a super-saturated, primarily single-phase material exhibiting an FCC microcrystalline structure.

Abstract: The present invention provides a process for the preparation of metal ion complexes, the process comprising contacting a metal in the form of particles with a chelating agent in solid form and, while the metal is in contact with the chelating agent, contacting the metal and chelating agent with an oxidising agent. The present invention also provides novel metal ion complexes. The invention further provides uses of the metal ion complexes.

Abstract: Techniques for data manipulation using a matrix multiplication engine using pipelining are disclosed. A first and a second matrix are obtained for matrix multiplication. A first matrix multiply-accumulate (MAC) unit is configured, where a first matrix element and a second matrix element are presented to the MAC unit on a first cycle. A second MAC unit is configured in pipelined fashion, where the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and where a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle. Additional MAC units are further configured within the processor in pipelined fashion. Multiply-accumulate operations are executed in pipelined fashion on each of n MAC units over additional k sets of m cycles.

Abstract: A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.

Abstract: The present disclosure is directed to multi-segment intraluminal guide wires including an elongate distal portion comprising a first metallic material (e.g., nitinol), an elongate proximal portion comprising a second metallic material (e.g., stainless steel). The distal and proximal portions may be directly joined together end to end by a solid-state weld joint. A diameter of the weld region surrounding the weld joint on either side of the weld joint may be reduced (e.g., ground down) relative to the diameter of the distal and proximal portions of the guide wire on either side of the weld region. A stiffness adjusting sleeve may be disposed over the weld joint so that a transition profile of bending stiffness across the weld region is gradual, rather than abrupt across the distal portion of the guide wire to the proximal portion of the guide wire. A polymer jacket may cover the sleeve and distal portion.

Abstract: A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.

Abstract: During operation, a system obtains a graph that includes a set of nodes representing users in an online network and a set of edges representing relationships or interactions between pairs of the nodes. Next, the system selects egos containing a subset of the users that are representative of a distribution of an attribute across the users. The system then generates clusters of users, such that each cluster contains an ego and alters selected from the ego's connections in the graph. The system further divides the clusters between a treatment group and a control group, exposes alters in the treatment group to a treatment variant of an A/B test, and exposes alters in the control group to a control variant of the A/B test. Finally, the system outputs a result of the A/B test.

Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A direct memory access (DMA) engine, coupled to the one or more processor clusters, is configured, wherein the DMA engine employs address generation across a plurality of tensor dimensions. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. DMA addresses are generated based on the unique address space descriptors and the common address space descriptor. Memory using two or more of the DMA addresses that were generated is accessed, where the two or more DMA addresses enable processing within the one or more processor clusters.

Abstract: Embodiments are directed to radiopaque implantable structures (e.g., stents) formed of cobalt-based alloys that comprise cobalt, chromium, tungsten, and nickel, and methods for their manufacture. Tungsten is present above its solubility limit (about 15%) at ambient temperature, but is still only present as a super-saturated, primarily single-phase material exhibiting an FCC microcrystalline structure.

Abstract: The present invention relates to compositions comprising a metal, a metal aggregation inhibitor, and a colour changing agent. The metal is bindable to the colour changing agent to provide a change in colour on binding and/or release thereof.

Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.

Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.

Abstract: Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A direct memory access (DMA) engine, coupled to the one or more processor clusters, is configured, wherein the DMA engine employs address generation across a plurality of tensor dimensions. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. DMA addresses are generated based on the unique address space descriptors and the common address space descriptor. Memory using two or more of the DMA addresses that were generated is accessed, where the two or more DMA addresses enable processing within the one or more processor clusters.