Abstract: Glitch propagation is modelled during circuit design simulation by determining the input duration of each signal pulse received by a cell, utilizing the input duration to distinguish whether the input pulse is a glitch or a valid data signal pulse, assigning a cell-type-specific scaling factor value to each signal pulse identified as a scalable glitch, calculating a scheduled output duration by multiplying the scaling factor value and the input duration, and controlling the cell by scaling (i.e., limiting or reducing) the duration of a corresponding output pulse signal to the scheduled output duration. Each cell-type-specific scaling factor value corresponds to observed glitch decaying effect characteristics of corresponding cells in physical IC devices. A simulation tool automatically assigns glitch scaling modules to each cell of a circuit design, whereby the glitch scaling process is performed on each cell during simulation.