Abstract: The disclosed method for recovering optical properties of transparent substrates may include performing a post-etching annealing process on a transparent substrate. The method may also include applying a plasma treatment to the transparent substrate, performing an atomic layer etching treatment on the transparent substrate, and/or performing a cleaning process. Various other methods, devices, and systems are also disclosed.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: Disclosed herein are techniques for fabricating a straight or slanted surface-relief grating with a uniform or non-uniform grating depth. According to certain embodiments, a gray-tone photoresist includes a novolac resin, a diazonaphthoquinone (DNQ) dissolution inhibitor, and one or more crosslinking agents for crosslinking the novolac resin at an elevated temperature to increase a glass transition temperature of the gray-tone photoresist and/or lower an etch rate of the gray-tone photoresist. After gray-tone photo exposure and development, the gray-tone photoresist is baked at the elevated temperature to crosslink. The crosslinked gray-tone photoresist has a higher density and a higher glass transition temperature, and thus would not become flowable to cause ripples or other surface roughness during the etching.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.